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specs/port/tools/jtag/link_relay.t27 is Zig, not t27, and has never compiled #4559
Description
specs/port/tools/jtag/link_relay.t27 is named .t27 and is written in Zig. It has never compiled, on any backend, since it landed in #4533 today.
$ t27c gen-c specs/port/tools/jtag/link_relay.t27
Error: Compile error: Expected LBrace, got KwStruct ('struct') at line 104:43
Same failure on gen-rust, gen-verilog and gen.
What is actually in the file
Zig, end to end — not a t27 spec with a few Zig-isms in it:
| construct | count | t27 |
|---|---|---|
@intCast(x as T) |
23 | no cast needed; declare the width |
try std.testing.expect(...) |
14 | assert(...) in a test "..." block |
?struct{ role: []u8, idcode: u32 } |
1 | no optionals; a struct with an ok field |
m.tms(&[1,1,0,0]) |
9 | free functions, array literal without & |
while (i < n) : (i += 1) |
6 | while (i < n) { ... i = i + 1; } |
.{ .role = r, .idcode = i } |
1 | DieRole { ... } |
null, .is_null(), .unwrap(), .or(0) |
6 | the ok field |
Why nothing caught it
tools/check_specs_generate.py short-circuits: it reports "baseline entries that now generate" and returns before reaching "specs that newly do not generate". specs/ml/optimizer/adamw.t27 was fixed by #4540 and left in the baseline, so every run stopped at adamw and never looked at link_relay. Pruning adamw is what made this visible.
The seven test blocks never ran either, and one of them asserts a wrong constant: ir_val2 == 0x1F3DF for IDCODE at idx=1 on a 3-chain. The arithmetic is 0x1F000 | (0x0E << 6) | 0x1F = 0x1F39F. A test that cannot compile cannot be wrong out loud.
Границы
In scope: rewriting the spec in t27 so it typechecks clean and generates on all four backends, and pruning the stale adamw baseline line that was hiding it.
Out of scope, deliberately, each its own defect:
undefinedlowers to{0};, which is not valid C.read_user1.t27in this same directory is classed Working and its generated C also fails to compile, 6 errors, for exactly this reason. A backend defect across every spec that stubs a body, not this file's.check_specs_generate.pyshort-circuits. The ordering bug above is why this went unseen for a day; it will hide the next one too.--update-baselineprunes but refuses to add, which is correct and is why this could not be blessed away.- The
emit-bitexactgate triggers onpull_requestonly, so master accumulates these and they surface on unrelated PRs.
Activity
fix(specs): the JTAG relay spec was Zig, not t27, and had never compiled
fix(specs): three ported specs were Zig and Python, and the gate repo…