Four advisory gates are red on master for inherited reasons, one cause per pull request #5497

Each of these workflows stops at its first failing step, so CI shows one cause per gate and hides the rest. Running every step of all four on master 756bcffc shows the following. None of it comes from an open pull request; the same rows fail on master.

Duplicate Body Ratchet (dupe-ratchet.yml)

11 groups are in no ledger:

• digest_for (8) and githubCiDeps_checkRuns_impl (5) are scanner false positives: a declaration ending in ; borrows the next function's body.
• forwardPass (3) copies one empty-result literal inside specs/hslm/forward_pass.t27.
• rng_int_range (2) is two stub bodies in specs/port/trinity/src/tri/gen_fuzz.t27 (return undefined;), ported from a Zig file that calls std.Random.DefaultPrng.
• bytes_eq, session_status_str, led_config, validate_led_config, startup_config, update_oscillator_chain, shift_ir are copies across two files. They cannot share one body while use a::b; generates no import (use a::b; generates no import, so no spec can reuse a function from another spec #4610).

Corpus Ratchet (corpus-ratchet.yml)

• 3 files gained an assertionless test: specs/igla/coder/pipeline.t27 (144 -> 145), specs/port/fpga/verilog/ternary_mac_synth.t27 (0 -> 1), specs/port/fpga/vivado/gf16_matmul_top.t27 (0 -> 1).
• tri types ratchet: 15 new type-name conflicts (BezierCurve, ConfigEntry, CounterState, Gate, Issue, JtagShiftRegister, ModuleInterface, Mpsse, OscillatorState, Path, Point, Pool, PullRequest, RSAKeyPair, StatusResponse) and 3 ledger rows that no longer conflict (AdamWConfig, JitCache, ParseResult).
• tri types classified: the same 18 names.
• The corpus ratchet itself has not been reached on CI since these steps went red. Its result is measured in the PR that addresses it.

Spec Guards (spec-guards.yml)

• check_seal_currency.py: 588 stale generated-code hashes on master (CI run 36945833011).
• published_figures.py --check: 9 figures drifted.
• Ring/spec drift and the converged-pair differential run after the seal step and are measured in their own PRs.

Emit Bit-Exact Gate (emit-bitexact-gate.yml)

• check_specs_generate.py: 15 specs newly fail to generate.
• tools/verify_emit_bitexact.py was overwritten by the salvage commit 38eac3a (Commit the board files for the AX7203 XOR training run (scratchpad/board/bpmet) #4812, "commit what the turn left uncommitted"). The new file imports MAXWIDTH from gft_backprop_microcode, which has never defined it, so the step fails at import. The previous version passes on today's master, including yosys synthesis of every listed topology.
• verify_multitarget.py --require fails locally; the cause is measured in its own PR.

How it is being fixed

One pull request per cause, each with Refs to this issue. No ledger is raised to hide a defect. Where a ledger has to move (a copy that #4610 makes unavoidable, a resolved row), the pull request names the rows and the reason, as #4497 did.

Boundary

• specs/hslm/forward_pass.t27
• specs/igla/coder/pipeline.t27
• specs/port/fpga/verilog/ternary_mac_synth.t27
• specs/port/fpga/vivado/gf16_matmul_top.t27
• specs/port/trinity/src/tri/gen_fuzz.t27
• tools/verify_emit_bitexact.py