gen-verilog: a refused on_clock entry point leaves no comment in the .v file #5963

Problem

t27c gen-verilog writes the in-file // ENTRY POINT REFUSED -- ... comment only inside the // NO DATA PORTS branch. An on_clock handler whose parameters are refused (no derivable width, e.g. a slice) while the module still exposes a mutable var as an output port takes the other branch, so the generated .v file says nothing about the refusal. Since #5955 the refusal is reported on stderr, but the file itself is silent. For on_comb the comment is written (the module is port-less in that case).

Reproduction (head of #5955, ddcef8a71)

module slice_clock;

var acc : u8 = 0

fn on_clock(xs: []u8) {
    acc = acc + 1;
}

t27c gen-verilog slice_clock.t27: stderr prints t27c gen-verilog: ENTRY POINT REFUSED -- xs: []u8, exit 0, and the module header is (clk, rst_n, en, ready, output reg [7:0] acc) with no refusal comment anywhere in the output.

Expected

The same comment on_comb gets, written by the same code, whenever an entry point is refused.

Part of #5905. Stacked on #5955.