specs: uart_echo_top.t27 models LUT1 INIT 2'b01 as pass-through, but INIT=01 is an inverter #6561

Found while porting uart_detect_top (#4969, PR #6534).

A LUT1 with INIT 2'b01 outputs 1 when I0=0 and 0 when I0=1, so it is an inverter. uart_echo_top.t27 models it as a pass-through. The sibling port specs/port/fpga/vivado/uart_detect_top.t27 models it correctly.

Success Criteria

• The model in uart_echo_top.t27 inverts, and a test with I0=0 and with I0=1 asserts the inverted value.
• t27c test-report on the spec prints FAIL 0.

Boundary

• specs/port/fpga/vivado/uart_detect_top.t27

User Scenarios

• Given a LUT1 with INIT 2'b01 in uart_echo_top.t27, When the spec is compiled and tested with I0=0, Then the output must be 1 (inverted).
• Given a LUT1 with INIT 2'b01 in uart_echo_top.t27, When the spec is compiled and tested with I0=1, Then the output must be 0 (inverted).

Requirements

• FR-001: The model in specs/port/fpga/vivado/uart_echo_top.t27 MUST invert the input when INIT=2'b01.
• FR-002: The spec MUST include test cases asserting inverted output for both I0=0 and I0=1.

Success Criteria

• t27c test-report specs/port/fpga/vivado/uart_echo_top.t27 prints FAIL 0 and exits 0.
• The spec contains at least 2 test cases covering I0=0 and I0=1 with inverted expectations.