t27c gen-verilog: a function whose only parameter is an array drops the input and uses the test's argument name #6562

Found while porting uart_detect_top (#4969, PR #6534).

t27c gen-verilog miscompiles a function with a single array parameter: the generated module drops the input port and references the caller's (test's) argument name instead of the parameter.

Success Criteria

• A minimal .t27 regression spec with a one-array-parameter fn generates Verilog whose port list contains the parameter, and iverilog compiles it.
• Existing gen-verilog fixtures unchanged.

Boundary

• bootstrap/src/compiler.rs

User Scenarios

• Given a .t27 spec defining a function fn process(arr: [4]u8) -> u8 and a test calling it with a local array let data = [4]u8{...}; process(data)
• When running t27c gen-verilog on that spec
• Then the generated Verilog module for process has an input port named arr (not data), and iverilog compiles the output without "port not found" errors

Requirements

• FR-001: The Verilog backend MUST emit the function's formal parameter name as the input port when the function has exactly one parameter of array type
• FR-002: The Verilog backend MUST NOT substitute the caller's argument name for the formal parameter name in the generated module's port list
• FR-003: The regression spec added for this fix MUST compile with t27c gen-verilog and the resulting Verilog MUST pass iverilog -Wall (exit 0)
• FR-004: Existing gen-verilog fixture tests in the repository MUST continue to pass unchanged