gen-verilog W459 binds a test-local array to a module array: ternary_isa 6 -> 7 elaboration errors #6685

Problem

FPGA Build / fpga-conformance on master counts 7 iverilog elaboration errors in ternary_isa, one more than the ratchet baseline (6).

Cause

901ed4f (#4594) added a test to specs/fpga/ternary_isa.t27 with a test-local given stages = [...]. W459 binds a [N]T parameter to the identifier used at its call sites, test blocks included, and takes that test-local for a module array. The generated pipeline_total_latency loses input [263:0] stages; and indexes an undeclared name: Unable to bind wire/reg/memory stages[...].

This is a defect in bootstrap/src/compiler.rs, not in the spec. Renaming the test-local in the spec would hide it from the ratchet without fixing it.

Proposed patch (prose; it is hand-written Rust, so it needs the owner's owner-approved-foreign label)

PR #5948 already carries it: W459 binds only when the identifier is a module-level const or var; anything else is passed by value (the #1745 part-select path). Test first in bootstrap/tests/verilog_array_param_test_local.rs, FROZEN_HASH and the 15 moved seals refreshed. With it, ternary_isa returns to 6.

Interim

Until that lands, the elaboration baseline records ternary_isa 7 as a known gap that points here. When the compiler fix lands, the row must go back to 6.

Boundary

• specs/fpga/ternary_isa.t27
• bootstrap/src/compiler.rs
• bootstrap/tests/verilog_array_param_test_local.rs

User Scenarios

• Given a spec with a test-local given stages = [...] array and a module parameter declared as [N]T, When the Verilog backend (W459) emits the module, Then the test-local array must not be bound as the module array parameter; the generated Verilog must declare input [263:0] stages; and elaborate without "Unable to bind wire/reg/memory stages" errors.

Requirements

• FR-001: The Verilog backend in bootstrap/src/compiler.rs MUST bind a [N]T parameter identifier only when that identifier resolves to a module-level const or var; test-local bindings MUST be passed by value (part-select path).
• FR-002: A new test bootstrap/tests/verilog_array_param_test_local.rs MUST be added that compiles a spec containing a test-local array with the same name as a module array parameter and asserts the generated Verilog elaborates with iverilog (exit 0).

Success Criteria

• cargo test --test verilog_array_param_test_local exits 0
• t27c specs/fpga/ternary_isa.t27 --target verilog produces Verilog that iverilog elaborates with exit 0
• The fpga-conformance ratchet for ternary_isa returns to 6 elaboration errors (down from 7)