corpus ratchet: gft_dup3_jtag and check_catalog_integrity ports carry assertionless tests #7473

The Corpus ratchet is red on master. The step "No new assertionless spec test" (tools/check_assertionless_spec_tests.py, #3141) fails:

specs/port/fpga/verilog/gft_dup3_jtag.t27  0 -> 1
specs/port/tools/check_catalog_integrity.t27  0 -> 5

Both files came from port PRs that landed placeholder tests:

• a3d5b41 (Port fpga/verilog/gft_dup3_jtag.v (Verilog, 1 module) to specs/port/fpga/verilog/gft_dup3_jtag.t27 #7211) ported fpga/verilog/gft_dup3_jtag.v as a module whose only test is assert true.
• 5a1c6e4 (Port tools/check_catalog_integrity.py (Python, 4 functions) to specs/port/tools/check_catalog_integrity.t27 #6875) ported tools/check_catalog_integrity.py with stub function bodies and five assert true tests (check_dangling_source, check_missing_spec, check_family_collapse, main_self_check_flag, main_clean_catalog).

The fix gives these tests real asserts that a mutant fails. They are not deleted and the baseline is not re-blessed.

• gft_dup3_jtag: state the readout the bitstream was built with: the v3 capture word {16'hA5A5, 4'd3, 6'd16, c_init, c_self, c_comm, c_ind, beat, ok}, the shift-register seed 0xA5A5343C it equals when every clause holds, the JTAG shift, the four clause predicates, the sticky rule, the settle counter and the two counters.
• check_catalog_integrity: model the Python check's six rules (dangling source, missing neighbour row or file, collapsed family, alias, lost former_name, lost golden-section rule) over the planted tree its --self-check builds. Port that self-check's eight controls and main's exit-code wiring (T85b).

Verify on the t27c lab: gen for zig, verilog, c and rust; t27c test-report; and tri mutate spec.

Boundary

• specs/port/fpga/verilog/gft_dup3_jtag.t27
• specs/port/tools/check_catalog_integrity.t27
• fpga/verilog/gft_dup3_jtag.v
• tools/check_assertionless_spec_tests.py
• tools/check_catalog_integrity.py

User Scenarios

• Given the Corpus ratchet step "No new assertionless spec test" runs on master, When it scans specs/port/fpga/verilog/gft_dup3_jtag.t27 and specs/port/tools/check_catalog_integrity.t27, Then it reports zero assertionless tests (exit 0) instead of the current 1 and 5.

Requirements

FR-001: The spec specs/port/fpga/verilog/gft_dup3_jtag.t27 MUST replace its single assert true test with real assertions covering the v3 capture word {16'hA5A5, 4'd3, 6'd16, c_init, c_self, c_comm, c_ind, beat, ok}, the shift-register seed 0xA5A5343C, the JTAG shift sequence, the four clause predicates, the sticky rule, the settle counter, and the two counters.

FR-002: The spec specs/port/tools/check_catalog_integrity.t27 MUST replace its five assert true tests (check_dangling_source, check_missing_spec, check_family_collapse, main_self_check_flag, main_clean_catalog) with real assertions that model the Python check's six rules (dangling source, missing neighbour row or file, collapsed family, alias, lost former_name, lost golden-section rule) over the planted tree built by --self-check, including the eight controls and main's exit-code wiring (T85b).

FR-003: Both specs MUST retain their tests (not delete them) and MUST NOT re-bless the baseline; the new assertions MUST be strong enough that a mutant would fail.

Success Criteria

• tools/check_assertionless_spec_tests.py run on the two spec files exits 0 and reports 0 assertionless tests for each
• t27c test-report on specs/port/fpga/verilog/gft_dup3_jtag.t27 shows all tests pass for zig, verilog, c, and rust targets
• t27c test-report on specs/port/tools/check_catalog_integrity.t27 shows all tests pass for zig, verilog, c, and rust targets
• tri mutate spec on both spec files reports at least 1 mutant killed per replaced assertion (total ≥ 6 mutants killed across both files)