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t27b: the AArch64 instruction encoders are a t27 spec (port slice of #6198) #7531
Port slice of #6198 (t27b written in t27), under #6063 and #5980.
cli/t27b/src/a64.rs (1067 lines of hand-written Rust) holds the AArch64 instruction encoders that t27b's code generator and JIT call: each function builds one 32-bit instruction word from register numbers and immediates. Those encoders, the condition/extend/shift/logical-op enums, the register and access-kind constants and the two patch helpers (adrp_patch, add_imm_patch) move into specs/tri/t27b/a64.t27. They reach cli/t27b through t27c gen-rust as gen/rust/tri/t27b/a64.rs and are mounted like check_budget.
What stays hand-written in a64.rs, and why:
impl Cond { invert, name, from_bits } -- name returns &'static str and from_bits indexes a table; both are disassembler support.
bitmask_imm (the logical-immediate search, returns Option<(u32, u32, u32)>, loops over u64 rotations), mov_imm (pushes into &mut Vec<u32>), and logic_imm (calls bitmask_imm, then the generated logic_imm_word).
Expected words come from the current Rust and from the 173 clang-checked cases in cli/t27b/tests/encoder.rs. A sample is cross-checked against LLVM's assembler (zig cc -c, then objdump -d).
Mutation check: every numeric literal in the encoder half of the spec is perturbed, one per copy, and t27c test-report must go red.
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t27b: the A64 instruction encoders come from specs/tri/t27b/a64.t27 (C…
t27b: the Mach-O object layout and bytes are a t27 spec (Closes #7526) (