Epic: t27b overnight improvement loop (2026-10-10) -- weak spots, competitors, plan #8326

A 15-minute loop works through this plan without a person in the loop. Each tick:

1. Checks for anomalies and repairs them.
2. Merges green PRs.
3. Moves one item forward.
4. Records what it learned in the skills.
   Rules that do not change: new logic is written in .t27; hand-written code in other languages only shrinks (policy: hand-written code in any language but t27 may only shrink (Closes #8227) #8236); gen/ is generated; every PR closes its own issue.

Where t27b stands (lab, master 0fca4bd, 2026-10-09)

• Reference passes: 1238 specs.
  • t27b passes 1143 of them with checks.
  • 56 pass vacuously, down from 152 thanks to seven batches of real tests.
  • 21 are blocked.
  • 0 mismatches.
• Generated share of t27b: about 26%. Hand Rust: about 16k lines in src and 8.3k in tests; lower.rs is being ported.
• Releases: t27b v0.1.0 (signed receipts), t27c 0.5.x.

Weak spots (self-critical)

1. Most of t27b is still hand-written (epic: t27b in t27 -- port the backend and its tooling from Rust/Python into .t27 #6198). Every coverage fix used to add glue; since 2026-10-09 the net must be <= 0.
2. The oracle is one x86 Zig build. Undefined behaviour "passes" there (t27b: array literals the reference prints as @constCast(&[_]E{ ... }) get one writable static per type and value, from a t27 plan (Closes #7680) #7694); only the native arm64 ratchet cross-checks it, and that check is not required.
3. The ledger drifts. Specs land without rows, and master's native ratchet goes red for everyone (t27b ratchet: UNLISTED blames the PR that adds the spec, not every later PR #8321, t27b: rows for the 6 specs that landed after #8289 without one #8322).
4. One lab is a bottleneck.
   • Master runs pre-empt lane requests.
   • Admission drops any request the lab has not fetched yet (t27b-lab: a request whose commit the lab has not fetched yet waits instead of being dropped #8320).
   • Receipts come after the merge, not before.
5. Gates are inherited. A red non-required check on master makes every PR UNSTABLE, and auto-merge is refused.
6. The workstation is fragile. core.hooksPath flipped to an absolute path twice and stalled all commits (loop health: detect and repair the anomalies that stalled the 2026-10-09 lanes #8325).
7. Encodings are checked only by our own tests, not against ARM's ISA spec (t27b encoder: check a64.t27 encodings against ARM's machine-readable ISA spec #8323).
8. The remaining 21 blocked specs are a long tail: i128 at run time, anytype, generics, [N]T, ?void, anonymous structs, Allocator. Three of them are deliberate refusals or reference bugs.

Competitors and what to take from them

• Cranelift (Wasmtime). ISLE lowering rules are verified against authoritative ISA semantics by Crocus, then Arrival (OOPSLA 2025), which found real bugs and a CVE. To take: check our encoder against ARM's spec (t27b encoder: check a64.t27 encodings against ARM's machine-readable ISA spec #8323).
• Copy-and-patch JITs (CPython; Lua; R at VMIL 2025). To take: a stencil tier generated from .t27 could replace the hand JIT and interpreter (t27b JIT: a copy-and-patch tier generated from .t27 stencils (research) #8324).
• Zig's self-hosted backends. The x86 backend is the default in Debug; aarch64 is a from-scratch rewrite in progress. This is why our reference runs on x86 only, and why the native arm64 ratchet matters.
• CompCert / CakeML set the bar for verified compilation. Our answer is signed receipts plus DDC (t27b lab: signed corpus receipts and a base-vs-head equivalence check (Merkle roots over verdicts and asm outputs) #7576, verified: a signed DDC receipt of t27core and T732's verdict over its routes (Closes #7699) #7706). The next step is a DDC route with an independent frontend (C4 of EPIC: golden reference language -- the compiler sieve (TNF-style theorems), and t27 passes it #6488, epic: self-host t27c -- rewrite the compiler from Rust into t27 #5980).

Plan

Ordered by unblock value per token.

Process

• t27b-lab: a request whose commit the lab has not fetched yet waits instead of being dropped #8320 lab admission waits for an unfetched commit (.t27 only)
• t27b: rows for the 6 specs that landed after #8289 without one #8322 ledger rows for the 6 unlisted specs
• t27b ratchet: UNLISTED blames the PR that adds the spec, not every later PR #8321 UNLISTED attribution, or native ratchet required
• loop health: detect and repair the anomalies that stalled the 2026-10-09 lanes #8325 loop-health checks as a tri command written in .t27

Port (#6198)

• lower.rs lanes: t27b: the source-text rules of lower.rs move to specs/tri/t27b/source_text.t27 (Closes #8248) #8252 landed, t27b: the body walks of lower.rs move to specs/tri/t27b/ast_walk.t27 (Closes #8249) #8258 open
• next: codegen.rs, main.rs, ir.rs

Coverage (#6063)

• t27b: / and % of two integer constants fold at compile time, as Zig folds them (Closes #7812) #8027, t27b: @intCast as an array index or a slice bound takes Zig's usize, from int_cast_plan.t27 (Closes #7902) #7905, t27b: a local bound to an array repeat [v; n] and passed as [N]T is that array, as gen-zig prints .{ v } ** n (Closes #7909) #7912 land, followed by post-merge receipts
• three tested vacuous batches: tools-cards 14, agents-skills 8, logic 8
• blocked tail: i128 (t27b: run-time 128-bit integers (type i128 at run time in phi_f64_literals, eval_arith and source_text) #7915), Allocator (t27b: a std.mem.Allocator that is stored but never called (specs/port/trinity/src/tri/gen_regression.t27) #7917), list literal in an invariant (t27b: a list literal indexed inside an invariant is a comptime tuple in the reference (ternary_gates.t27, formats.t27) #7930)

Research

• t27b encoder: check a64.t27 encodings against ARM's machine-readable ISA spec #8323 encoder against ARM spec
• t27b JIT: a copy-and-patch tier generated from .t27 stencils (research) #8324 copy-and-patch tier

Self-host (#5980)

• P4: other backends of t27core
• P5: drop the Rust seed (enables the independent DDC route)

Budget

On 2026-10-09 at 20Z the weekly usage was 89%; it resets 2026-10-10 12Z.

• Until the reset the loop runs cheap ticks: health, merge-when-green, and the agents already running.
• Above 95%, it pauses itself and resumes after the reset.

See #6488, #6063, #6198, #5980.

User Scenarios

• Given the overnight improvement loop is configured, When the 15-minute tick fires, Then anomalies are checked and repaired, green PRs are merged, one plan item advances, and learnings are recorded in skills
• Given the weekly usage budget is below 95%, When the loop runs its cheap ticks, Then health checks, merge-when-green, and agent tasks execute without pause
• Given the weekly usage budget exceeds 95%, When the loop would exceed the threshold, Then it pauses itself and resumes after the weekly reset at 2026-10-10 12Z

Requirements

• FR-001: The loop MUST run every 15 minutes without human intervention
• FR-002: Each tick MUST check for anomalies and repair them
• FR-003: Each tick MUST merge green PRs
• FR-004: Each tick MUST advance exactly one plan item
• FR-005: Each tick MUST record learnings in the skills
• FR-006: The loop MUST pause when weekly usage exceeds 95% and resume after reset
• FR-007: New logic MUST be written in .t27 files only
• FR-008: Hand-written code in other languages MUST only shrink
• FR-009: Every PR MUST close its own issue
• FR-010: Lab admission MUST wait for unfetched commits per t27b-lab: a request whose commit the lab has not fetched yet waits instead of being dropped #8320
• FR-011: Ledger rows MUST exist for all specs per t27b: rows for the 6 specs that landed after #8289 without one #8322
• FR-012: Loop health checks MUST be implemented as a tri command in .t27 per loop health: detect and repair the anomalies that stalled the 2026-10-09 lanes #8325

Success Criteria

• scripts/tri_loop/t27b.py runs a full tick and exits with exit 0
• specs/tools/tri/loop.t27 compiles with t27c and exits with exit 0
• specs/tools/tri/competitors.t27 compiles with t27c and exits with exit 0
• 56 vacuous specs reduced to 0 through real tests
• 21 blocked specs resolved or documented as deliberate refusals
• Ledger has rows for 6 previously unlisted specs
• Native arm64 ratchet required for merge (not optional)

Boundary

• specs/tools/tri/loop.t27
• specs/tools/tri/competitors.t27
• scripts/tri_loop/t27b.py
• cli/tri/src/competitors.rs