E2c: eth_reply.t27 -- the receipt as a unicast UDP datagram to the requester (AX7203) #8388

Part of #8327 (E2: TRI-NET node over UDP on the AX7203). Refs #6655. Follows #8333 (EthRx, merged in #8370) and #8356 (TrinetNode, merged in #8373).

Goal

A t27 spec for the transmit half of the job link: when TrinetNode has a receipt, send it as one unicast UDP datagram to the host that sent the request, on the same PHY byte stream EthBeacon drives (one byte per 125 MHz clock, tx_en and txd).

Where we are

• specs/fpga/eth_beacon.t27 sends a constant broadcast frame with a constant IPv4 checksum; it is confirmed on the bench AX7203.
• specs/fpga/eth_rx.t27 latches the sender's MAC, IP and port in src_mac, src_ip, src_port at every frame.
• specs/fpga/trinet_node.t27 raises resp_v for one clock with r_y, r_st, r_n, r_tag, 59 clocks after the frame that started the job. By then EthRx may already hold the next frame's sender, so the sender must be taken when the job starts, not when the receipt is ready.

Boundary

• New: specs/fpga/eth_reply.t27, .trinity/seals/fpga_EthReply.json.
• Changed: specs/fpga/trinet_node.t27 gains one output, j_go, 1 for one clock when a job starts (its seal moves with it). No other behaviour of TrinetNode changes.
• Ledgers as the gates need them (t27b row, elaboration row, duplicate baseline for the CRC functions every RTL module carries).
• Out of bounds: EthRx, EthBeacon, wrappers, XDC, the TRI-NET protocol.

User Scenarios & Testing

1. A receipt for a request from 192.168.1.101:50000 (MAC 02:00:00:00:00:99) goes out as one frame to that MAC, IP and port, from 02:27:00:00:00:01, 192.168.1.227:27028, with the 19-byte payload A5 Y STATUS NONCE[4] NODE_ID[4] TAG[8] (little-endian fields) and a correct IPv4 checksum and FCS.
2. The sender is the one latched when the job started, even if another frame from another host arrived before the receipt was ready.
3. A receipt that arrives while a frame is still on the line, or inside the inter-frame gap, is counted as dropped and not sent half-way.
4. Between frames the line is idle (tx_en = 0) for at least 12 clocks.

Requirements

• R1. Frame: preamble 7 x 0x55, SFD 0xD5, then 61 data bytes (14 Ethernet, 20 IPv4 with total length 47, 8 UDP with length 27 and checksum 0, 19 payload), then the FCS (CRC-32, least significant byte first). No padding is needed (61 >= 60).
• R2. The IPv4 checksum depends on the destination address and is computed in registered steps during the preamble, so no adder chain sits in front of a byte the line needs.
• R3. Reference frames come from an independent computation (Python struct, RFC 791, zlib.crc32), not from the spec.
• R4. Hardware semantics as in E2a: eth_rx.t27 -- receive path for UDP datagrams to the TRI-NET node (AX7203) #8333 and E2b: trinet_node.t27 -- TRI-NET MAC32 job core with SipHash-2-4 receipts (AX7203) #8356; closes 125 MHz out of context.

Success Criteria

• t27c test-report specs/fpga/eth_reply.t27 passes, 0 vacuous, covering scenarios 1-4; the reference frame's checksum and FCS are asserted.
• TrinetNode's tests still pass with j_go, and a test shows j_go rises exactly when a job starts.
• The generated RTL, simulated against the independent frames, matches byte for byte.
• gen-verilog closes 125 MHz in nextpnr-xilinx out of context on three seeds.
• Sealed with the compiler built from the PR tree; CI green on the final SHA.