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gen-verilog: a function brought in by use is called but never defined, and gen-verilog exits 0 #8769
Description
Defect under the self-host epic (see #5980). Found while trying to generate an on-die self-test for specs/queen/actors_hw.t27, the FPGA lane of gHashTag/trios#1763.
Problem
t27c gen-verilog lowers only the functions declared in the spec it is given. A function the spec brings in with use is called in the emitted RTL, but its body is never emitted, and gen-verilog exits 0. yosys then refuses the file. The Zig path compiles and tests the same spec.
So a spec cannot reuse another spec's logic in hardware. The only ways around it are to copy the bodies, which the duplicate-bodies gate rejects, or to instantiate the other module, which gen-verilog cannot do either (see #8660).
Minimal repro (t27c 0.5.2, master c31c059)
specs/xa/lib.t27:
// SPDX-License-Identifier: Apache-2.0
module XaLib;
pub fn twice(x: u8) -> u8 { return x + x; }
test twice_works { assert_eq(twice(3), 6); }
specs/xa/user.t27:
// SPDX-License-Identifier: Apache-2.0
module XaUser;
use xa::lib::twice;
var out : u8 = 0
fn on_clock(v: u8) { out = twice(v); }
test uses_twice { out = 0; on_clock(4); assert_eq(out, 8); }
| command | result |
|---|---|
t27c gen-verilog specs/xa/user.t27 |
exit 0. The clocked block reads out <= twice(v);. The only function in the file is __mul_noop. |
yosys -p "read_verilog user.v; synth_xilinx -family xc7 -top XaUser" (0.63) |
user.v:55: ERROR: Can't resolve function name '\twice'. |
t27c test-report specs/xa/user.t27 --specs-dir specs |
1 test, 0 FAIL, 1 runtime assert |
Acceptance
gen-verilogemits each function that the module's synthesizable code reaches throughuseas a Verilogfunctioninside the module, souser.vsynthesizes with yosys. The imported function must read its own module's constants; compare use (Zig backend): an importer's constant silently replaces a same-named constant the imported function reads #8342, where the Zig backend lets a same-named constant of the importer replace them.- Until that lands,
gen-verilogexits non-zero and names the imported function it cannot lower, instead of writing a file that yosys rejects. gen-verilog cannot instantiate device primitives (STARTUPE2, BUFG, BSCANE2, LUTs), so on-die designs need a hand-written wrapper #8660 asks the same for an undeclared callee.
What it blocks
The lane needs an on-die self-test of the actor engine: a generated module that runs actors_hw.t27's test vectors through its hw_ decisions and reports a verdict over JTAG. If used functions were lowered, that module could call the decisions directly. Without it, the module has to instantiate QueenActorsHw, which needs module instances (#8660). The JTAG primitives (STARTUPE2, BUFG, BSCANE2) need #8660 on either route.
🤖 Generated with Claude Code
Boundary
specs/queen/actors_hw.t27specs/xa/lib.t27specs/xa/user.t27
Activity
t27b: verilog -- a Verilog path decided in .t27 plans: extern modules…
tri-claw commentedon Oct 11, 2026
The Queen cannot take this issue yet. A bee starts only on an issue whose body has every section below, and this one lacks:
- specs/x.t27); without it the Queen reserves nothing and no bee can take the issueFR-001: ... MUST ...She tried to write them 2 times and could not (last: refused: refused paths: specs/xa/lib.t27, specs/xa/user.t27). Add them and the next round takes it. The rule is
specs/policy/issue_shape.t27.dmitrii-f-t27 commentedon Oct 15, 2026
Technical evidence for this issue, from work on PR #9636 and a local prototype. No approval of any code is requested.
The defect is real and silent. gen-verilog of the unchanged specs/port/scripts/gen_w709.t27 defines
function indent,elem_x,elem_y,build_level,build_treeand the rest. gen-verilog of specs/port/scripts/gen_w698.t27 after its helpers moved behinduse port::scripts::gen_w_tree;defines onlyfunction generate; every helper definition is gone and the test names survive as comments. The command exits 0.It produced a false green on spec(port): share tree helpers across eight gen_w ports (Closes #9633) #9636. The corpus ratchet reported an unexpected pass for gen_w698 [gen-verilog] and the suite expectation was lowered 83 to 82. A clean local suite ratchet (82 of 82, unexpected fail 0 and pass 0) does not detect the lost definitions. That removal is conditional and unjustified until this issue is fixed.
A local partial candidate (worktree codex/verilog-use-8769, uncommitted, not published) passes the positive case: user.t27 importing
twiceandbiasedgetstwice,biased,wrap_addand the libraryBIAS 3; iverilog exits 0 and yosys proc/opt/check -assert exits 0 with 0 problems. Before it, iverilog exited 2 and yosys said Can't resolve functiontwice.The candidate is wrong in three ways:
BIAS = 9captures the library'sBIAS = 3. A direct testbiased(4) == 7prints PROBE 13, FAILED, expected 7 got 13 (vvp exits 0 with FAILED, so read the output, not the exit code).icarus-simulate userstill exits 1 (unknowntwice,biased,on_clock), andcompile_verilog_for_simulation_atand the path-lesscompile_verilogused by suite.rs still get the raw source, so a change only in the main.rs handler leaves the corpus and seal paths broken.foreign-budgethook denies the staged main.rs (16 added, 3 deleted, +13). No label or exception overrides that budget, so owner approval alone would not make this diff acceptable.A correct fix needs the central compile paths, a negative proof for same-name capture, and no growth of hand-written Rust debt. The existing base exceptions for main.rs (#6509, #6446) are narrow and are not approval for this change.
Dmitrii Fedorov (@dmitrii-f-t27)
ci(dupe): record the eight STEP1/STEP2 copies in the ledger (Refs #9631)
ci(dupe): turn duplicate-bodies green -- share gen_w tree helpers, re…