E2f: generate the TRI-NET node's 100 Mb/s top from t27; only the PLL, I/O and BSCANE2 primitives stay extern #8875

Part of #8327. Follows #8770 (the board logic in t27, PR #8772).

Why

#8772 first carried a hand-written top, fpga/verilog/trinet_eth_top.v (37 lines) and trinet_eth_top.xdc (25 lines), with a tools/policy/foreign-exceptions.txt entry. The foreign-line budget of own-language (owner rule 2026-10-09: no hand-written code in any language but t27 may grow, no label lifts it) rejects both files, so #8772 now carries only the t27 logic (specs/fpga/{mdio_100m,rgmii_100,jtag_status}.t27). The top that wires the six modules is this issue. The last revision with the hand-written top is a1177e121 (fpga/verilog/trinet_eth_top.v), which ran on the board (10000/10000 keyed jobs).

What

Generate the top of the 100 Mb/s TRI-NET node from t27, the way specs/queen/actors_hw_top.t27 is generated by t27b verilog (#8820, #8830):

1. specs/fpga/xc7_primitives.t27 (fpga: the 7-series primitives declared once, in specs/fpga/xc7_primitives.t27 (Closes #8832) #8833) gains the missing extern primitives: IBUFDS, PLLE2_ADV and ODDR (BUFG and BSCANE2 are already there).
2. specs/fpga/trinet_eth_top.t27 holds the wiring of Mdio100m, Rgmii100, EthRx, TrinetNode, EthReply and JtagStatus: the MDIO pins and PHY reset, the RGMII nibble core between RXC/RXD and TXC/TXD, the PLL (RXC 25 MHz to clk at 0 and 180 degrees), the ODDR that forwards TXC, the LEDs and the BSCANE2 USER3 status chain. No logic beyond wiring and constants.
3. The only cells that stay outside t27 are the Xilinx primitives themselves (PLL, I/O buffers, BUFG, ODDR, BSCANE2): extern declarations, no hand-written Verilog module.
4. The pin constraints (25 lines of .xdc at a1177e121) are generated from t27 or kept out of the repo; no hand-written foreign line is added.

Done when

• t27b verilog specs/fpga/trinet_eth_top.t27 writes the top; the diff adds no hand-written foreign line and no foreign-exceptions.txt entry; own-language (both steps) is green.
• Tests in the spec check the wiring against reference values computed outside t27 first; seals saved with the tree's own t27c; t27c test-report has 0 failures and 0 vacuous passes.
• A bitstream built from the generated top closes timing (clk 25 MHz, c200 200 MHz) and answers 10000/10000 keyed jobs on the AX7203 (SRAM only), with the run log in the PR.

Dmitrii Fedorov (@dmitrii-f-t27)

User Scenarios

• Given the specs/fpga/xc7_primitives.t27 file lacks IBUFDS, PLLE2_ADV, and ODDR extern declarations, When t27b verilog processes specs/fpga/trinet_eth_top.t27, Then the generated top-level Verilog includes proper extern references to these Xilinx primitives without hand-written Verilog modules.
• Given the six modules Mdio100m, Rgmii100, EthRx, TrinetNode, EthReply, and JtagStatus exist in t27, When specs/fpga/trinet_eth_top.t27 wires them together with the PLL, ODDR, LED assignments, and BSCANE2 USER3 chain, Then t27b verilog specs/fpga/trinet_eth_top.t27 emits a complete top-level module containing only wiring and constants.
• Given the tools/policy/foreign-exceptions.txt currently has an entry for the hand-written trinet_eth_top.v, When the generated top replaces the hand-written top, Then the foreign-exceptions entry is removed and own-language passes with zero foreign-line growth.

Requirements

• FR-001: specs/fpga/xc7_primitives.t27 MUST declare IBUFDS, PLLE2_ADV, and ODDR as extern primitives alongside existing BUFG and BSCANE2.
• FR-002: specs/fpga/trinet_eth_top.t27 MUST wire Mdio100m, Rgmii100, EthRx, TrinetNode, EthReply, and JtagStatus including MDIO pins, PHY reset, RGMII nibble core, PLL (RXC 25 MHz → clk 0°/180°), ODDR forwarding TXC, LEDs, and BSCANE2 USER3 status chain.
• FR-003: The generated top MUST contain no logic beyond wiring and constants; all Xilinx primitive instances (PLL, I/O buffers, BUFG, ODDR, BSCANE2) MUST remain extern declarations.
• FR-004: No hand-written Verilog file (fpga/verilog/trinet_eth_top.v) MUST be added to the repository; no entry for it MUST exist in tools/policy/foreign-exceptions.txt.
• FR-005: Pin constraints (XDC) MUST be generated from t27 or kept out of the repo; no hand-written .xdc file MUST be added.

Boundary

• specs/fpga/xc7_primitives.t27
• specs/fpga/trinet_eth_top.t27