Port compiler.rs Verilog name predicates (is_icarus_builtin, is_simple_tuple_type) to specs/compiler/verilog_names.t27 through t27o #9115

• Compiler::is_icarus_builtin(name): t27o converts it, and its oracle passes (8 generic vectors: add "__mul_noop" and near misses from the hand Rust).
• VerilogCodegen::is_simple_tuple_type(ty): t27o converts it, but the output does not compile until t27o: output t27c refuses -- a char pattern miscompiled, a transitive splice, same_text under gen-rust, []const []const u8 #9103.

User Scenarios

• Given a call to __mul_noop in a spec lowered to Verilog, when ast_is_icarus_lowerable checks callees, then is_icarus_builtin answers from the generated module.
• Given the type (u8, u16), when the Verilog backend asks is_simple_tuple_type, then the generated module answers true, and for (a: u8) it answers false.

Requirements

• FR-001: specs/compiler/verilog_names.t27 MUST define both functions with t27o's bodies (text equality through tri::t27b::type_text's same), with tests calling each by name on vectors printed by the hand Rust.
• FR-002: The two hand fns MUST become one-line calls into bootstrap/gen/rust/compiler/verilog_names.rs, mounted by #[path].
• FR-003: The PR MUST satisfy the owner's port rule: net <= 0 foreign lines, generated output byte-identical over the corpus, cargo test --release equal to master, FROZEN_HASH re-computed.

Success Criteria

• t27c test-report specs/compiler/verilog_names.t27 reports 0 FAIL and 0 vacuous.
• The diff touches compiler.rs only inside the fns named in this issue, apart from the one #[path] mount block at the top of the file.
• cargo test --release in bootstrap/ gives the same pass and fail counts and failure names as clean master.

Region lines to be added once the merge-side region check is live (see #9062).

Boundary

• specs/compiler/verilog_names.t27
• bootstrap/gen/rust/compiler/verilog_names.rs
• .trinity/seals/compiler_VerilogNames.json
• bootstrap/stage0/FROZEN_HASH