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t27b: emit_kit -- one home for the writers' shared helpers (Refs #9994) - #10065

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Oct 17, 2026
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Master's duplicate-bodies gate is red after #10047. That PR merged at its head before its duplicate-bodies fix was pushed, so specs/tri/t27b/ts_emit.t27 still repeats 18 helper bodies of verilog_emit.t27 word for word. This PR lands that fix on top of master.

What changes

  • New specs/tri/t27b/emit_kit.t27. The shared helpers now live once, in this module, with four tests of their own:
    • the byte and number writers (put_bytes, put_dec, put_ind, dec_len);
    • to_front and line_near;
    • the scope and name resolver (resolve, in_scope, parent_of, child_holding, param_index, param_name_lo, param_name_hi);
    • the symbol encoding (sym_of, sym_at);
    • the test-tree builders (tnode, tmeta, holds).
  • Both writers drop their copies and use tri::t27b::emit_kit by name. Their generated Rust and their seals are regenerated.
  • The ternary_matmul row leaves tools/duplicate_bodies_baseline.txt. That duplicate group is already gone on master, and the gate refuses a ceiling left above the real count. Blessing only lowers the ledger and adds no slack.
  • A ledger row for emit_kit goes into docs/reports/t27b_expectations.json, and the t27b README gets one line about the module.

Why not import the other writer whole

A whole-module use of verilog_emit from ts_emit does not work. The use splicer counts words inside string literals as references. So the string "export function" in ts_emit pulls in verilog_emit's fn function, and the generated-Rust typecheck then refuses it against ts_emit's own param_type and stmts.

Measured on the Railway lab, on top of master 896d87b

  • test-report: emit_kit 4/4, ts_emit 4/4, verilog_emit 7/7, with 0 vacuous passes.
  • dupe_scan: ok after the bless.
  • t27b ts and t27b verilog: byte-identical output and exit codes before and after, on all 2095 specs (4190 of 4190 runs).
  • gen-rust: 0 UNRESOLVED in both writers.

Refs #9994

🤖 Generated with Claude Code

#10047 merged at its head before this fix reached the branch, and master's
duplicate-bodies gate went red: ts_emit.t27 repeats 18 helper bodies of
verilog_emit.t27 word for word (byte writers, to_front, line_near, the
scope and name resolver, the symbol encoding, the test-tree builders).
They now live once, in specs/tri/t27b/emit_kit.t27, with tests of their
own, and both writers `use` it by name.

A whole-module `use` of verilog_emit from ts_emit does not work: the
splice counts words inside string literals as references, so ts_emit's
"export function" pulls verilog_emit's fn `function`, and the generated
Rust typecheck refuses it against ts_emit's own param_type and stmts.

The ledger also loses its ternary_matmul row: that group is gone on
master and the gate refuses a ceiling left above the real count.

Measured on the Railway lab, on top of master 896d87b: test-report
emit_kit 4/4, ts_emit 4/4, verilog_emit 7/7, 0 vacuous; dupe_scan ok
after the bless; t27b ts and t27b verilog print byte-identical output and
exit codes before and after on all 2095 specs (4190 of 4190). Generated
writers and the three records regenerated there.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Generated at: 2026-10-17 18:02:41 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 50
PRs with All Checks Green 0
READY 0
FAILING 50
PENDING 0
NO CHECKS YET 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=e769ef021713 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@gHashTag
gHashTag enabled auto-merge (squash) October 17, 2026 18:04
@gHashTag
gHashTag merged commit a18d7ee into master Oct 17, 2026
33 of 37 checks passed
dmitrii-f-t27 added a commit to dmitrii-f-t27/t27 that referenced this pull request Oct 17, 2026
Conflict only in .trinity/seals/t27b_T27bVerilogEmit.json. verilog_emit.t27 merged cleanly
(master moved the shared writer helpers to emit_kit.t27, used by verilog_emit; the pin
declaration code stays). gen/rust/tri/t27b/verilog_{emit,plan}.rs equal this tree's t27c
gen-rust; the seal is re-saved with it.

Checks with this tree: seals of verilog_emit, verilog_plan, eth_top_ax7203 and
xc7_primitives verify; t27c test-report and t27b test 8/8, 15/15, 2/2 (and 2/2); t27b
verilog writes the board top with its 22 pin attributes, synthesizable part unchanged.
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