fix(t27b): a port named after a t27 keyword is spelled with a trailing underscore (Closes #10061)

.trinity/seals/t27b_T27bAstShape.json

@@ -1,13 +1,13 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+f787afb",
+  "built_by": "t27c-bootstrap@0.5.2+063da04",
   "closure": [
     {
       "spec": "specs/tri/t27b/ast_scan.t27",
       "spec_hash": "sha256:e6f28b9bceb1b0fd5315e80a66beed3d791311dacf2bd5d5b7cbc79250d8b385"
     },
     {
       "spec": "specs/tri/t27b/verilog_plan.t27",
-      "spec_hash": "sha256:a52dbb4524173c54e19d205ee72b8a1544da978df82cc15a92341c7cad9ba428"
+      "spec_hash": "sha256:c7eb1749b322a318ec71a2544172783a77361cf9a2083b88fcc7afd3c5a44708"
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
@@ -18,7 +18,7 @@
   "module": "T27bAstShape",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-17T17:33:08Z",
+  "sealed_at": "2026-10-17T18:12:16Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
   "spec_hash": "sha256:fef40e3e7885265523c48d4a936c033bbc929b80dbf3ec06f79332dd63834134",
   "spec_path": "specs/tri/t27b/ast_shape.t27",

.trinity/seals/t27b_T27bEmitKit.json

@@ -1,9 +1,9 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+9b160b143",
+  "built_by": "t27c-bootstrap@0.5.2+063da04",
   "closure": [
     {
       "spec": "specs/tri/t27b/verilog_plan.t27",
-      "spec_hash": "sha256:a52dbb4524173c54e19d205ee72b8a1544da978df82cc15a92341c7cad9ba428"
+      "spec_hash": "sha256:c7eb1749b322a318ec71a2544172783a77361cf9a2083b88fcc7afd3c5a44708"
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
@@ -14,7 +14,7 @@
   "module": "T27bEmitKit",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-17T17:54:26Z",
+  "sealed_at": "2026-10-17T18:12:16Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
   "spec_hash": "sha256:7a31a1e4383104b0b59b2a339ccbe6d87eb69f56f28e5bff95befa18b0dba795",
   "spec_path": "specs/tri/t27b/emit_kit.t27",

.trinity/seals/t27b_T27bTsPlan.json

@@ -1,9 +1,9 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+a1b584b29",
+  "built_by": "t27c-bootstrap@0.5.2+063da04",
   "closure": [
     {
       "spec": "specs/tri/t27b/verilog_plan.t27",
-      "spec_hash": "sha256:6178c276f6928f211b1cb65f470a93a5fcfbb11119bad7a26030072d777e8e70"
+      "spec_hash": "sha256:c7eb1749b322a318ec71a2544172783a77361cf9a2083b88fcc7afd3c5a44708"
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
@@ -14,7 +14,7 @@
   "module": "T27bTsPlan",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-17T17:23:01Z",
+  "sealed_at": "2026-10-17T18:12:17Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
   "spec_hash": "sha256:d046e9702ec1a0a9db5b9d8666e0bc8f7f38361f1bc320e5d9420931f7887e46",
   "spec_path": "specs/tri/t27b/ts_plan.t27",

.trinity/seals/t27b_T27bVerilogEmit.json

@@ -1,5 +1,5 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+9b160b143",
+  "built_by": "t27c-bootstrap@0.5.2+063da04",
   "closure": [
     {
       "spec": "specs/tri/t27b/emit_kit; // byte writers, to_front, line_near, resolve and symbols, test trees.t27",
@@ -11,27 +11,27 @@
     },
     {
       "spec": "specs/tri/t27b/verilog_plan.t27",
-      "spec_hash": "sha256:a52dbb4524173c54e19d205ee72b8a1544da978df82cc15a92341c7cad9ba428"
+      "spec_hash": "sha256:c7eb1749b322a318ec71a2544172783a77361cf9a2083b88fcc7afd3c5a44708"
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
-  "gen_hash_c": "sha256:24f73f039c0ba7fa8a523d428bb49d715d43cbbb784f12d9ff08cde73b3035e1",
-  "gen_hash_rust": "sha256:827184630e8660cf8a16957f96bffd91a136365061ce2b7ad32287a0380421fc",
-  "gen_hash_verilog": "sha256:cc260a30a0d7d86562173ec7e5037d4e12b388faaf267a083783b72f24356760",
-  "gen_hash_zig": "sha256:5970a4a3ef8dfa8c720bee5f09573e5914ce023f6c7d86caecc080dd81a23d1a",
+  "gen_hash_c": "sha256:d4a0c1d16b2e75c1d7028eae7133c8af8359b1e90ada94289435881e2c31a2dc",
+  "gen_hash_rust": "sha256:daa741c306509d8baabb4130273593065066784a63697e693d5287bca45ce7d8",
+  "gen_hash_verilog": "sha256:81f1f5903b2800ed2d684e7ceb986eb7106e8ec9f6978d329afe7313b1565a3c",
+  "gen_hash_zig": "sha256:abf0fbf7e8028b15f30438cae0a89bb32a2b5257576e7f1d2f1027958b1d6d6f",
   "module": "T27bVerilogEmit",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-17T17:54:27Z",
+  "sealed_at": "2026-10-17T18:12:17Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
-  "spec_hash": "sha256:e34f866a304927d4ff6b2eca2485c74551490d6dd79aae40001249debc14cc76",
+  "spec_hash": "sha256:b28baac32b8d291619dfe2664fe4167287f6705ec901fa0e87200ee95523a84d",
   "spec_path": "specs/tri/t27b/verilog_emit.t27",
   "tests": {
     "failed": 0,
     "failing": [],
     "forced": false,
-    "passed": 7,
-    "total": 7,
+    "passed": 8,
+    "total": 8,
     "vacuous": 0
   },
   "toolchain": {

.trinity/seals/t27b_T27bVerilogPlan.json

@@ -1,29 +1,29 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+f787afb",
+  "built_by": "t27c-bootstrap@0.5.2+063da04",
   "closure": [
     {
       "spec": "specs/tri/t27b/ast_walk.t27",
       "spec_hash": "sha256:6653bee4e36f576c6b04d29b537ad52481c959e98b922257f48f3c0d4cf809e3"
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
-  "gen_hash_c": "sha256:88edabc42fca646e9a444d9f82370d78ecb67a5afa554f949f57fb4eb573a7f4",
-  "gen_hash_rust": "sha256:b02233d200b6cad6d160305768928911509d98199f0aee9d208bf9f14a1e9065",
-  "gen_hash_verilog": "sha256:c490c6a07fb43b4ae5fd69949d9725baf10e9332277667b7365ce040d605280d",
-  "gen_hash_zig": "sha256:30a577020d433ae2de867124d570b67a3f4799d03909c83c38f3f723a33d3a55",
+  "gen_hash_c": "sha256:5b61c4481375289a5498e39d2f7ea3ea430fdc8d100fc0d6faa3428f67919518",
+  "gen_hash_rust": "sha256:5feafbe5476ebc8fb7f3abfb05bd0225bc8fd14c3f3bc6b479421845a052d422",
+  "gen_hash_verilog": "sha256:62cec2367aab19770b0e706753ee7905e30050c2fb52b807bfcf909cc6c674e0",
+  "gen_hash_zig": "sha256:3d3bc805bd698fc8e6470c867572bcdedf3d090f9f59bc5c8b1f1b3b760f2637",
   "module": "T27bVerilogPlan",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-17T17:33:05Z",
+  "sealed_at": "2026-10-17T18:12:18Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
-  "spec_hash": "sha256:a52dbb4524173c54e19d205ee72b8a1544da978df82cc15a92341c7cad9ba428",
+  "spec_hash": "sha256:c7eb1749b322a318ec71a2544172783a77361cf9a2083b88fcc7afd3c5a44708",
   "spec_path": "specs/tri/t27b/verilog_plan.t27",
   "tests": {
     "failed": 0,
     "failing": [],
     "forced": false,
-    "passed": 14,
-    "total": 14,
+    "passed": 16,
+    "total": 16,
     "vacuous": 0
   },
   "toolchain": {

gen/rust/tri/t27b/verilog_emit.rs

@@ -1,6 +1,6 @@
 // Generated from .t27 spec
 // DO NOT EDIT — generated by t27c
-// NOT LOWERED BY THIS BACKEND: 7 test(s), 0 invariant(s), 0 function(s) with no body.
+// NOT LOWERED BY THIS BACKEND: 8 test(s), 0 invariant(s), 0 function(s) with no body.
 // This backend emits declarations only. The spec's checks live in
 // the Zig and Verilog outputs; do not read this file as verified.
 
@@ -15,12 +15,13 @@ pub const M_TEST: u8 = 3;
 pub const M_TBFUNC: u8 = 4;
 
 pub fn put_name(out: &mut [u8], at: usize, text: &[u8], a: usize, b: usize) -> usize {
-    if verilog_keyword(&text[(a) as usize..(b) as usize]) {
+    let e: usize = name_end(text, a, b);
+    if verilog_keyword(&text[(a) as usize..(e) as usize]) {
         let mut q: usize = put_text(out, at, "\\");
-        q = put_bytes(out, q, text, a, b);
+        q = put_bytes(out, q, text, a, e);
         return put_text(out, q, " ");
     }
-    return put_bytes(out, at, text, a, b);
+    return put_bytes(out, at, text, a, e);
 }
 
 pub fn put_range(out: &mut [u8], at: usize, t: i64) -> usize {
@@ -2999,6 +3000,8 @@ pub const ROLE_PARAM: u8 = 2;
 
 pub const ROLE_PORT: u8 = 1;
 
+pub const T27_KEYWORDS: [&'static str; 29] = ["and", "bench", "break", "const", "continue", "else", "enum", "false", "fn", "for", "if", "in", "invariant", "let", "module", "or", "pragma", "pub", "return", "struct", "switch", "test", "true", "try", "use", "using", "var", "void", "while"];
+
 pub const TY_BAD: i64 = -1;
 
 pub const TY_BOOL: i64 = 65;
@@ -3350,6 +3353,13 @@ pub fn meta_word(meta: &[u8], i: usize, w: usize) -> usize {
     return u32_at(meta, ((i * META) + (w * 4)));
 }
 
+pub fn name_end(text: &[u8], a: usize, b: usize) -> usize {
+    if (((b > (a + 1)) && (text[((b - 1)) as usize] == 95)) && t27_keyword(&text[(a) as usize..((b - 1)) as usize])) {
+        return (b - 1);
+    }
+    return b;
+}
+
 pub fn op_bitwise(s: &[u8]) -> bool {
     return ((same(s, "&") || same(s, "|")) || same(s, "^"));
 }
@@ -3535,6 +3545,17 @@ pub fn steps_up(nodes: &[u8], text: &[u8], s: usize, va: usize, vb: usize) -> i6
     return cc;
 }
 
+pub fn t27_keyword(s: &[u8]) -> bool {
+    let mut j: usize = 0;
+    while (j < 29) {
+        if same(s, T27_KEYWORDS[(j) as usize]) {
+            return true;
+        }
+        j = (j + 1);
+    }
+    return false;
+}
+
 pub fn tie_folds(s: &[u8], v: u64) -> bool {
     return ((same(s, "rst_n") || same(s, "en")) && (v != 0));
 }

gen/rust/tri/t27b/verilog_plan.rs

@@ -1,6 +1,6 @@
 // Generated from .t27 spec
 // DO NOT EDIT — generated by t27c
-// NOT LOWERED BY THIS BACKEND: 14 test(s), 0 invariant(s), 0 function(s) with no body.
+// NOT LOWERED BY THIS BACKEND: 16 test(s), 0 invariant(s), 0 function(s) with no body.
 // This backend emits declarations only. The spec's checks live in
 // the Zig and Verilog outputs; do not read this file as verified.
 
@@ -820,6 +820,26 @@ pub fn verilog_keyword(s: &[u8]) -> bool {
     return false;
 }
 
+pub const T27_KEYWORDS: [&'static str; 29] = ["and", "bench", "break", "const", "continue", "else", "enum", "false", "fn", "for", "if", "in", "invariant", "let", "module", "or", "pragma", "pub", "return", "struct", "switch", "test", "true", "try", "use", "using", "var", "void", "while"];
+
+pub fn t27_keyword(s: &[u8]) -> bool {
+    let mut j: usize = 0;
+    while (j < 29) {
+        if same(s, T27_KEYWORDS[(j) as usize]) {
+            return true;
+        }
+        j = (j + 1);
+    }
+    return false;
+}
+
+pub fn name_end(text: &[u8], a: usize, b: usize) -> usize {
+    if (((b > (a + 1)) && (text[((b - 1)) as usize] == 95)) && t27_keyword(&text[(a) as usize..((b - 1)) as usize])) {
+        return (b - 1);
+    }
+    return b;
+}
+
 pub const PT: &'static str = "i<16+=1body<=+jcontinue_expr";
 
 pub const PT2: &'static str = "i<16+=1body<=+jundefinedxxxx";

specs/tri/t27b/verilog_emit.t27

@@ -37,14 +37,16 @@ pub const M_TBFUNC : u8 = 4;
 // Writing bytes.
 // ----------------------------------------------------------------------------------------------------------
 
-/// Writes the name text[a .. b], as an escaped identifier (`\wait `) when it is a Verilog keyword.
+/// Writes the name text[a .. b]: without the trailing `_` of a t27 keyword (`in_` is `in`, name_end), and as
+/// an escaped identifier (`\wait `) when what is left is a Verilog keyword.
 pub fn put_name(out: []u8, at: usize, text: []const u8, a: usize, b: usize) -> usize {
-    if (verilog_keyword(text[a .. b])) {
+    const e : usize = name_end(text, a, b);
+    if (verilog_keyword(text[a .. e])) {
         var q : usize = put_text(out, at, "\\");
-        q = put_bytes(out, q, text, a, b);
+        q = put_bytes(out, q, text, a, e);
         return put_text(out, q, " ");
     }
-    return put_bytes(out, at, text, a, b);
+    return put_bytes(out, at, text, a, e);
 }
 
 /// Writes the range of a scalar type, `[W-1:0] `, or nothing for one bit.
@@ -2096,6 +2098,75 @@ test numbers_ranges_literals_and_names_are_spelled {
     assert n4 == 6 and out[0] == 92 and out[5] == 32;
     const n5 : usize = put_name(out[0 .. 64], 0, "xseed", 1, 5);
     assert n5 == 4 and holds(out[0 .. 64], 4, "seed");
+    // a t27 keyword with its `_`: the keyword; one that is a Verilog keyword too is then escaped
+    const n6 : usize = put_name(out[0 .. 64], 0, "xin_", 1, 4);
+    assert n6 == 2 and out[0] == 105 and out[1] == 110;
+    const n7 : usize = put_name(out[0 .. 64], 0, "for_", 0, 4);
+    assert n7 == 5 and holds(out[0 .. 64], 5, "\\for ");
+    // and a name that is no keyword keeps its `_`
+    const n8 : usize = put_name(out[0 .. 64], 0, "data_", 0, 5);
+    assert n8 == 5 and holds(out[0 .. 64], 5, "data_");
+}
+
+test an_input_spelled_in_underscore_is_the_port_in {
+    // module P { const in_ : u8 = undefined; pub const out : u8 = in_; }
+    // text: P 0..1, in_ 1..4, u8 4..6, undefined 6..15, out 15..18, data_ 18..23, for_ 23..27
+    const tx : str = "Pin_u8undefinedoutdata_for_";
+    var nb : [360]u8 = undefined;
+    tnode(nb[0 .. 360], 0, K_MODULE, 5, 0, 1);
+    tnode(nb[0 .. 360], 1, K_CONST_DECL, 3, 1, 4);
+    vset(nb[0 .. 360], 1, F_TYPE, 4, 6);
+    tnode(nb[0 .. 360], 2, K_EXPR_IDENTIFIER, 3, 6, 15);
+    tnode(nb[0 .. 360], 3, K_CONST_DECL, 5, 15, 18);
+    vset(nb[0 .. 360], 3, F_TYPE, 4, 6);
+    tnode(nb[0 .. 360], 4, K_EXPR_IDENTIFIER, 5, 1, 4);
+    var mb : [80]u8 = undefined;
+    var i : usize = 0;
+    while (i < 5) {
+        tmeta(mb[0 .. 80], i, 0, i + 1);
+        i = i + 1;
+    }
+    tmeta(mb[0 .. 80], 3, FLAG_PUB, 4);
+    var wk : [80]u8 = undefined;
+    i = 0;
+    while (i < 80) {
+        wk[i] = 0;
+        i = i + 1;
+    }
+    var out : [4096]u8 = undefined;
+    const r : i64 = emit(nb[0 .. 360], tx, mb[0 .. 80], "", wk[0 .. 80], out[0 .. 4096]);
+    assert r > 0;
+    const n : usize = @intCast(r);
+    assert holds(out[0 .. 4096], n, "input  wire [7:0] in,") or holds(out[0 .. 4096], n, "input  wire [7:0] in\n");
+    assert holds(out[0 .. 4096], n, "assign out = in;");
+    assert !holds(out[0 .. 4096], n, "in_");
+    // negative control: an input `data_` is no keyword, and keeps its `_` at the port and at the read
+    vset(nb[0 .. 360], 1, F_NAME, 18, 23);
+    vset(nb[0 .. 360], 4, F_NAME, 18, 23);
+    i = 0;
+    while (i < 80) {
+        wk[i] = 0;
+        i = i + 1;
+    }
+    const r2 : i64 = emit(nb[0 .. 360], tx, mb[0 .. 80], "", wk[0 .. 80], out[0 .. 4096]);
+    assert r2 > 0;
+    const n2 : usize = @intCast(r2);
+    assert holds(out[0 .. 4096], n2, "input  wire [7:0] data_");
+    assert holds(out[0 .. 4096], n2, "assign out = data_;");
+    // `for_` is the port `for`, which is a Verilog keyword too: escaped, at the port and at the read
+    vset(nb[0 .. 360], 1, F_NAME, 23, 27);
+    vset(nb[0 .. 360], 4, F_NAME, 23, 27);
+    i = 0;
+    while (i < 80) {
+        wk[i] = 0;
+        i = i + 1;
+    }
+    const r3 : i64 = emit(nb[0 .. 360], tx, mb[0 .. 80], "", wk[0 .. 80], out[0 .. 4096]);
+    assert r3 > 0;
+    const n3 : usize = @intCast(r3);
+    assert holds(out[0 .. 4096], n3, "input  wire [7:0] \\for ");
+    assert holds(out[0 .. 4096], n3, "assign out = \\for ;");
+    assert !holds(out[0 .. 4096], n3, "for_");
 }
 
 test a_clocked_counter_lowers_to_a_register_and_an_always_block {