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19 changes: 12 additions & 7 deletions .trinity/seals/AdamW.json
Original file line number Diff line number Diff line change
@@ -1,14 +1,19 @@
{
"gen_hash_c": "sha256:c01ec3973f0a92519fd5bf1490d014ed9651d4cb0f4a89669b288661a85aa9ec",
"gen_hash_rust": "sha256:0010ce0e41a962f8db2e94baf5515a99b5312d3ef74f54ade99c42ebb65a6274",
"gen_hash_verilog": "sha256:ebecfc4c499455c39a38af49f4a9ac544e70c4452685d9583db2392044160964",
"gen_hash_zig": "sha256:4ca45035d84b11fef4daa132ea6fde13935fa74f55ef8bdc9c322f7b460d26e0",
"gen_hash_c": "sha256:5e0e6de65832ccf6c4f64d7410fe24af093b2d3a137a17bf37edc8a10c75a75a",
"gen_hash_rust": "sha256:93895575b4e59283c27fc742a1261d832cc79706db435e7ca5ffc1466a63e0f0",
"gen_hash_verilog": "sha256:c7f2055f86cd0f47f00558cfd67c2b5170d8cefa72db2a9a22798f57bf5c2878",
"gen_hash_zig": "sha256:a5225b8c6ab539841efc6bfe8bb875fac265068d0fc8019370f1c14eb7728685",
"module": "AdamW",
"ring": 12,
"sealed_at": "2026-10-11T10:43:20Z",
"spec_hash": "sha256:1b8cb03ec9edccd4b26b996d4f789f3ab4fc3feaca5df97d75ee003dd26070b0",
"sealed_at": "2026-10-17T18:31:13Z",
"spec_hash": "sha256:b58a44f505aeb0bbbc664b8708d13c9399f73b714c6b22d0b46cc5d33e853be7",
"spec_path": "specs/ml/optimizer/adamw.t27",
"tests": {
"blocked": "does not compile: spec.zig:54:13: error: use of undeclared identifier 'allocate_array'"
"failed": 0,
"failing": [],
"forced": false,
"passed": 12,
"total": 12,
"vacuous": 0
}
}
29 changes: 19 additions & 10 deletions .trinity/seals/optimizer_AdamW.json
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
{
"built_by": "t27c-bootstrap@0.5.2+cc19d1fcd",
"built_by": "t27c-bootstrap@0.5.2+efe3c94",
"closure": [
{
"spec": "specs/base/types.t27",
Expand All @@ -10,24 +10,33 @@
"spec_hash": "sha256:57187e7afda1d88167b2af0382ad7f0623aa6b269ba020a78e3ffeebba1161bb"
},
{
"spec": "specs/numeric/gf16.t27",
"spec_hash": "sha256:2a33d77db23966331716955924d08e30d12a3af361067da0a2c7072b7f4b7b0d"
"spec": "specs/ml/arena_heap.t27",
"spec_hash": "sha256:dadb837793dbfaa2f313bb3dfebe92764fe23c96228e11c10b933958e9feb0bb"
},
{
"spec": "specs/ml/optimizer/adam.t27",
"spec_hash": "sha256:75f3d191b54ab786de3aa085164717813022eb8f403da12fe5b55c7bda8aa73f"
}
],
"config": "gen=c,rust,verilog,zig;tests=zig",
"gen_hash_c": "sha256:c01ec3973f0a92519fd5bf1490d014ed9651d4cb0f4a89669b288661a85aa9ec",
"gen_hash_rust": "sha256:0010ce0e41a962f8db2e94baf5515a99b5312d3ef74f54ade99c42ebb65a6274",
"gen_hash_verilog": "sha256:ebecfc4c499455c39a38af49f4a9ac544e70c4452685d9583db2392044160964",
"gen_hash_zig": "sha256:4ca45035d84b11fef4daa132ea6fde13935fa74f55ef8bdc9c322f7b460d26e0",
"gen_hash_c": "sha256:5e0e6de65832ccf6c4f64d7410fe24af093b2d3a137a17bf37edc8a10c75a75a",
"gen_hash_rust": "sha256:93895575b4e59283c27fc742a1261d832cc79706db435e7ca5ffc1466a63e0f0",
"gen_hash_verilog": "sha256:c7f2055f86cd0f47f00558cfd67c2b5170d8cefa72db2a9a22798f57bf5c2878",
"gen_hash_zig": "sha256:a5225b8c6ab539841efc6bfe8bb875fac265068d0fc8019370f1c14eb7728685",
"module": "AdamW",
"ring": 12,
"seal_schema": 2,
"sealed_at": "2026-10-11T10:43:20Z",
"sealed_at": "2026-10-17T18:31:13Z",
"sealed_by": "t27c-bootstrap@0.5.2",
"spec_hash": "sha256:1b8cb03ec9edccd4b26b996d4f789f3ab4fc3feaca5df97d75ee003dd26070b0",
"spec_hash": "sha256:b58a44f505aeb0bbbc664b8708d13c9399f73b714c6b22d0b46cc5d33e853be7",
"spec_path": "specs/ml/optimizer/adamw.t27",
"tests": {
"blocked": "does not compile: spec.zig:54:13: error: use of undeclared identifier 'allocate_array'"
"failed": 0,
"failing": [],
"forced": false,
"passed": 12,
"total": 12,
"vacuous": 0
},
"toolchain": {
"test_runner": "sha256:1982ae948e24d00c5d221ccec12dfce1eb01204b53e37b0f857f93b16d64629d",
Expand Down
5 changes: 4 additions & 1 deletion docs/reports/t27b_expectations.json
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@
"reference-bug": "the reference passes it for the wrong reason; t27b is right not to",
"n/a": "outside what t27b is for (say why in the PR that sets it)"
},
"max_not_pass": 28,
"max_not_pass": 31,
"entries": [
{"path": "specs/a/b_c.t27", "t27b": "pass"},
{"path": "specs/a_b/c.t27", "t27b": "pass"},
Expand Down Expand Up @@ -413,6 +413,8 @@
{"path": "specs/ml/activation/silu_swish_activation.t27", "t27b": "blocked", "blocker": "ExprCall(undeclared fn)", "reason": "unimplemented"},
{"path": "specs/ml/activation/softmax.t27", "t27b": "blocked", "blocker": "ExprCall(undeclared fn)", "reason": "unimplemented"},
{"path": "specs/ml/activation/tanh_activation.t27", "t27b": "blocked", "blocker": "ExprCall(undeclared fn)", "reason": "unimplemented"},
{"path": "specs/ml/arena_heap.t27", "t27b": "blocked", "blocker": "ExprCall(@mod)", "reason": "unimplemented"},
{"path": "specs/ml/file_io_contract.t27", "t27b": "blocked", "blocker": "ExprCall(@mod)", "reason": "unimplemented"},
{"path": "specs/ml/igla_champion_capsule.t27", "t27b": "blocked", "blocker": "ExprIdentifier(undeclared)", "reason": "unimplemented"},
{"path": "specs/ml/layers/avgpool2d_layer.t27", "t27b": "pass"},
{"path": "specs/ml/layers/batchnorm_layer.t27", "t27b": "blocked", "blocker": "ExprCall(undeclared fn)", "reason": "unimplemented"},
Expand All @@ -432,6 +434,7 @@
{"path": "specs/ml/loss/mse_loss.t27", "t27b": "pass"},
{"path": "specs/ml/optimizer/adagrad.t27", "t27b": "blocked", "blocker": "ExprCall(undeclared fn)", "reason": "unimplemented"},
{"path": "specs/ml/optimizer/adam.t27", "t27b": "blocked", "blocker": "ExprCall(undeclared fn)", "reason": "unimplemented"},
{"path": "specs/ml/optimizer/adamw.t27", "t27b": "blocked", "blocker": "ExprCall(undeclared fn)", "reason": "unimplemented"},
{"path": "specs/ml/optimizer/lamb.t27", "t27b": "blocked", "blocker": "ExprCall(undeclared fn)", "reason": "unimplemented"},
{"path": "specs/ml/optimizer/race_config.t27", "t27b": "blocked", "blocker": "ExprIdentifier(undeclared)", "reason": "unimplemented"},
{"path": "specs/ml/optimizer/rmsprop.t27", "t27b": "pass"},
Expand Down
1 change: 0 additions & 1 deletion docs/reports/type_conflicts.json
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,6 @@
"MigrationStep",
"ModuleInterface",
"Node",
"OptimizerStepResult",
"OscillatorState",
"Outputs",
"ParseError",
Expand Down
30 changes: 20 additions & 10 deletions specs/igla/own_model.t27
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,15 @@
; vocab-729 head and cross-entropy), its backward reaches the embedding, and every gradient is
; checked against a central difference; a mutant that drops one alpha fails 10 of the 46.
; Not in it then: the per-block VSA path, f32, and the trainer's STE update (shadow weights).
; - re-test on 2026-10-18, same t27c, lab checkout brought to master, after the PR that gave
; t27 a pure arena allocator and a file I/O contract (specs/ml/arena_heap.t27 10/10,
; specs/ml/file_io_contract.t27 12/12) and rewrote optimizer/adamw (#10077): adamw 12/12
; pass, 0 vacuous, its moment buffers carved from the arena. cross_entropy_loss 5/5, sgd 4/4,
; adam 4/4, lamb 4/4, nn/hslm (61/61 after the VSA PR) and hslm/forward_pass 14/14 still pass, so 7 of the 17
; compile. nn/attention ('PHI_CUBED_INV') and the nine coder specs stay BLOCKED. Cells 24 and
; 25 stay gaps: the arena and the file contract are specs of what t27c must lower, and t27c
; lowers neither (no heap, no file I/O, no `--backend ml`; that work waits for the owner's
; owner-approved-foreign label).
; - test on 2026-10-18, same t27c, after the PR that added the training step (STE, backward, data):
; nn/ternary_ste 26/26, nn/hslm_backward 15/15, nn/hslm_data 39/39 pass, 0 vacuous. The STE is
; the TWN quantizer (delta 0.7 * mean abs, alpha = mean abs of the kept weights), the
Expand All @@ -39,7 +48,7 @@
; (ctx 27, head_dim 3): its trit, bias and input gradients match a central difference to 1e-6
; and 20 steps cut the loss below half. hslm_data holds the curriculum, next-token batches and
; the MSLH header and layout, whose byte count equals hslm_step_10000.bin (4971796). Not in
; them: the STE on the whole 3-block model, file I/O, heap, the tokenizer, shuffle, AdamW.
; them: the STE on the whole 3-block model, the tokenizer, shuffle; AdamW, heap and file I/O are in the entry above.
; - re-test on 2026-10-18, same t27c, after the PR that added the VSA path: nn/hslm 61/61 tests
; pass, 12 invariants proved, 0 vacuous. Each block now runs the VSA stream of model.zig
; forwardTrain (bind, rotate, the PHI_INV gate, +0.1 * project(context) when it fires, the
Expand All @@ -58,11 +67,12 @@
; cell weighted the same; that weighting is a convention, not a measurement.

; THE ANSWER this map gives: HSLM was trained before, in Zig only (64 files); its best runs
; (PPL 2.96 at ctx 27) were wiped by EXP-002 and survive only in the ledger. In t27 the loss, three
; (PPL 2.96 at ctx 27) were wiped by EXP-002 and survive only in the ledger. In t27 the loss, four
; optimizers and the HSLM spec's forward and backward passes pass, and that spec is now the trained
; model, its VSA path included (see MEASURED); the ternary STE, the training step and the data
; and checkpoint layout now pass too, on a model slice and on bytes; the STE over the whole model,
; heap and file I/O and `t27c --backend ml` do not exist yet.
; heap and file I/O exist as pure t27 contracts (ml/arena_heap, ml/file_io_contract) that t27c does not
; lower, and `t27c --backend ml` does not exist.

; Not claimed: no model quality beyond the numbers in SOURCES; no GIF or MP4, stills only.
; phi^2 + 1/phi^2 = 3 | TRINITY
Expand Down Expand Up @@ -158,7 +168,7 @@ pub const SOURCES : [27]str = [
"trinity-training src/hslm, 64 Zig files",
"trinity data/wave9/worker-2/hslm_step_10000.bin",
"t27 specs/ml/loss/cross_entropy_loss.t27",
"t27 specs/ml/optimizer/{sgd,adam,lamb}.t27",
"t27 specs/ml/optimizer/{sgd,adam,adamw,lamb}.t27",
"t27 specs/nn/hslm.t27 and specs/hslm/forward_pass.t27",
"t27 specs/nn/hslm.t27 backward and nn/hslm_backward.t27 training step on a head slice, finite-difference checked",
"t27 specs/nn/ternary_ste.t27, 26 tests; whole-model shadow weights not yet",
Expand All @@ -167,7 +177,7 @@ pub const SOURCES : [27]str = [
"trinity-fpga b2bd5a30, 7682304/7682304 receipts",
"board-production-2dec.up.railway.app/state",
"t27 specs/port/trinity/fpga/openxc7-synth/ternary_matvec.t27",
"t27c test-report on 17 ML specs: 6 compile",
"t27c test-report on 17 ML specs: 7 compile",
"",
"",
"",
Expand All @@ -183,7 +193,7 @@ pub const MISSING : [27]str = [
"",
"",
"", "", "", "", "",
"heap allocation and file I/O lowered by t27c: neither exists",
"heap allocation and file I/O lowered by t27c: neither exists; ml/arena_heap.t27 and ml/file_io_contract.t27 are the contract it must meet",
"a t27c backend that lowers a model spec to a training binary: none exists",
"embeddings, head and weights in DDR3 on the board: they stay on the host",
""
Expand All @@ -200,11 +210,11 @@ pub const STATUS : [27]u8 = [4, 4, 4, 3, 3, 3, 3, 0, 0, 4, 4, 4, 4, 4, 4, 3, 3,
pub const LABELS : [27]str = ["1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23", "24", "25", "26", "27"];

/// Percent of each part that exists, estimated from its source (see the header). Never a status.
pub const PCT : [27]u8 = [60, 70, 80, 80, 60, 10, 50, 0, 0, 100, 100, 20, 80, 65, 95, 75, 55, 40, 70, 15, 60, 40, 35, 0, 0, 0, 50];
pub const PCT : [27]u8 = [60, 70, 80, 80, 60, 10, 50, 0, 0, 100, 100, 20, 80, 65, 95, 75, 55, 40, 70, 15, 60, 40, 41, 0, 0, 0, 50];

/// The t27c test-report counts the PRACTICE cells quote.
pub const ML_SPECS_MEASURED : i32 = 17;
pub const ML_SPECS_COMPILING : i32 = 6;
pub const ML_SPECS_COMPILING : i32 = 7;
pub const CODER_SPECS : i32 = 9;
pub const CODER_SPECS_COMPILING : i32 = 0;

Expand All @@ -223,7 +233,7 @@ pub const ROWS : [20]str = [
"64 Zig files; best PPL 2.96 at ctx 27",
"Those checkpoints were wiped",
"In t27: loss, optimizers, HSLM pass",
"6 of 17 ML specs compile on the lab",
"7 of 17 ML specs compile on the lab",
"0 of 9 IGLA CODER specs compile",
"1 published, 12 verified, 9 drafts",
"5 gaps, about 48 percent overall",
Expand Down Expand Up @@ -326,7 +336,7 @@ test the_compile_counts_are_the_measured_ones {
assert TEST_PASS[5] == false;
// the compile cell's percent is the measured share, truncated
const share : i32 = share_pct(ML_SPECS_COMPILING, ML_SPECS_MEASURED);
assert share == 35;
assert share == 41;
const p22 : i32 = @intCast(PCT[22]);
assert p22 == share;
assert share_pct(CODER_SPECS_COMPILING, CODER_SPECS) == 0;
Expand Down
2 changes: 1 addition & 1 deletion specs/igla/own_model_board.t27
Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@ pub const KEY_PCT : str = "pct";

pub const LENS_PCT : [3]u8 = [45, 70, 30];
pub const CELL_STATUS : [27]u8 = [4, 4, 4, 3, 3, 3, 3, 0, 0, 4, 4, 4, 4, 4, 4, 3, 3, 3, 4, 4, 5, 4, 3, 0, 0, 0, 3];
pub const CELL_PCT : [27]u8 = [60, 70, 80, 80, 60, 10, 50, 0, 0, 100, 100, 20, 80, 65, 95, 75, 55, 40, 70, 15, 60, 40, 35, 0, 0, 0, 50];
pub const CELL_PCT : [27]u8 = [60, 70, 80, 80, 60, 10, 50, 0, 0, 100, 100, 20, 80, 65, 95, 75, 55, 40, 70, 15, 60, 40, 41, 0, 0, 0, 50];

/// The size of the compact metrics object, in bytes, computed from the keys and values above.
pub const METRICS_BYTES : i32 = 624;
Expand Down
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