fpga(ax7203): ternary mat-vec over real tern-tc-9m weights in DDR3, UART receipt (Closes #10461)

.trinity/seals/fpga_FpgaBoardReceipt.json

@@ -0,0 +1,28 @@
+{
+  "built_by": "t27c-bootstrap@0.5.2+a86b691b1",
+  "closure": [],
+  "config": "gen=c,rust,verilog,zig;tests=zig",
+  "gen_hash_c": "sha256:a5d6d0e10fdc5fa09a780007cd144fc129cf4de77c7762a9212bf64240806f34",
+  "gen_hash_rust": "sha256:f2efc42ebb64bbf2210158576b10c0fc652339aab5e1dcadac5cfda11472d192",
+  "gen_hash_verilog": "sha256:173a361ae8759a6ba7228d792947d405fed05747a23a9fd76afc768a2cfc3c61",
+  "gen_hash_zig": "sha256:34f3ca54b36f64c4e2b122d50f3f6c506275a5cf895e2478fdb4f6b15478c4b7",
+  "module": "FpgaBoardReceipt",
+  "ring": 12,
+  "seal_schema": 2,
+  "sealed_at": "2026-10-18T13:56:40Z",
+  "sealed_by": "t27c-bootstrap@0.5.2",
+  "spec_hash": "sha256:34634f7251ed8b2a1539748dd9aa8dbdb263d7c039e8635d05eea70c7857ceb2",
+  "spec_path": "specs/fpga/board_receipt.t27",
+  "tests": {
+    "failed": 0,
+    "failing": [],
+    "forced": false,
+    "passed": 4,
+    "total": 4,
+    "vacuous": 0
+  },
+  "toolchain": {
+    "test_runner": "sha256:1982ae948e24d00c5d221ccec12dfce1eb01204b53e37b0f857f93b16d64629d",
+    "zig": "0.16.0"
+  }
+}

.trinity/seals/fpga_FpgaDdr3HeadBandwidth.json

@@ -1,17 +1,22 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+79126608b",
-  "closure": [],
+  "built_by": "t27c-bootstrap@0.5.2+a86b691b1",
+  "closure": [
+    {
+      "spec": "specs/fpga/board_receipt.t27",
+      "spec_hash": "sha256:34634f7251ed8b2a1539748dd9aa8dbdb263d7c039e8635d05eea70c7857ceb2"
+    }
+  ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
-  "gen_hash_c": "sha256:23ce13530186a4f63ca3f42565c4f3b5ef346c5f4a8d8ba2e8ba1f5fe0a6de0e",
-  "gen_hash_rust": "sha256:d61c73f5c49d32d0d11aeafd20abb948f6ab4e0fcab4bafe48f005f7c2f5d8de",
-  "gen_hash_verilog": "sha256:65e8b6194fd2f634281e7c493a3bcf609afdc8850c049c4e0c6da69c989750a1",
-  "gen_hash_zig": "sha256:d7b5263c8fdf4d0ca62310bffd53858e33fb44556eda898c929be756b53c9c66",
+  "gen_hash_c": "sha256:1b37e08fd08dbbc0645a49bc82a0dcc499e209d26f5e5734ae39d130f920fe58",
+  "gen_hash_rust": "sha256:9543f6cb7a6e90c6af7602df2c0c5373f88ca949b74e90742fce80a42c0baa7e",
+  "gen_hash_verilog": "sha256:c8408e1ad2d20562e6f624647dca216e9d06483006eefeba1ce57857dd3fad09",
+  "gen_hash_zig": "sha256:ed9f25e68b8a6a456ec6eda990b40bc89a2abf948e8b87e46910eacb7b6830a3",
   "module": "FpgaDdr3HeadBandwidth",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-18T09:08:23Z",
+  "sealed_at": "2026-10-18T13:56:41Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
-  "spec_hash": "sha256:59242e4bc9430d41386640efe931ac3996a02afcee1b5142451750a48d99fc89",
+  "spec_hash": "sha256:152bf98420d4c3919835eefdb3cad56c76cd80cbecc11e1bcb6616fc25dfdd04",
   "spec_path": "specs/fpga/ddr3_head_bandwidth.t27",
   "tests": {
     "failed": 0,

.trinity/seals/fpga_FpgaDdr3TernaryMatvec.json

@@ -0,0 +1,33 @@
+{
+  "built_by": "t27c-bootstrap@0.5.2+a86b691b1",
+  "closure": [
+    {
+      "spec": "specs/fpga/board_receipt.t27",
+      "spec_hash": "sha256:34634f7251ed8b2a1539748dd9aa8dbdb263d7c039e8635d05eea70c7857ceb2"
+    }
+  ],
+  "config": "gen=c,rust,verilog,zig;tests=zig",
+  "gen_hash_c": "sha256:af4d241ce9398f06df4527b2e7d8db1f81eeefa0c1298ec4be8840302236d92f",
+  "gen_hash_rust": "sha256:0f474fbf43039fa0da4932752897314fb70fddac664e0efbf3f98b535fae9895",
+  "gen_hash_verilog": "sha256:7dd8c000bec8d732ebf2538e289621bee1f3c1e751df53f583beaaddf349680a",
+  "gen_hash_zig": "sha256:d38c2a80429c2b66adc024d7723b227ccaf2f792259277196f3255ebd3cd0f44",
+  "module": "FpgaDdr3TernaryMatvec",
+  "ring": 12,
+  "seal_schema": 2,
+  "sealed_at": "2026-10-18T15:37:16Z",
+  "sealed_by": "t27c-bootstrap@0.5.2",
+  "spec_hash": "sha256:84b7de73ff2f1a8679ca83443e0dcb62c5f30677cebc3015850331811420c16a",
+  "spec_path": "specs/fpga/ddr3_ternary_matvec.t27",
+  "tests": {
+    "failed": 0,
+    "failing": [],
+    "forced": false,
+    "passed": 10,
+    "total": 10,
+    "vacuous": 0
+  },
+  "toolchain": {
+    "test_runner": "sha256:1982ae948e24d00c5d221ccec12dfce1eb01204b53e37b0f857f93b16d64629d",
+    "zig": "0.16.0"
+  }
+}

.trinity/seals/fpga_FpgaRcFilter.json

@@ -1,17 +1,22 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+9da2c5f",
-  "closure": [],
+  "built_by": "t27c-bootstrap@0.5.2+a86b691b1",
+  "closure": [
+    {
+      "spec": "specs/fpga/board_receipt.t27",
+      "spec_hash": "sha256:34634f7251ed8b2a1539748dd9aa8dbdb263d7c039e8635d05eea70c7857ceb2"
+    }
+  ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
-  "gen_hash_c": "sha256:345d70ff4a42876b9a38808fb16183e3026e436fe989ae8421da9e346bc07096",
-  "gen_hash_rust": "sha256:6321804010ff1127f915e0004f936d9a7002c01a525de42c539fe9e2595fd9be",
-  "gen_hash_verilog": "sha256:f8a97da90c082ad1ab84c132487152da1fe021c7f7be0537d970d6a6483c36de",
-  "gen_hash_zig": "sha256:5da6f0a60ae03e0ac806727e04bf0d2ae19e3d3589271de9b090bc4f91590fb8",
+  "gen_hash_c": "sha256:d1b54196aeea618074c6654c877e42a69687369fff6483f1d140c96c0553db76",
+  "gen_hash_rust": "sha256:044f3df98ab05033ac9202b689a0ff7a8e701e4c25a38d57d26ce40ec7718586",
+  "gen_hash_verilog": "sha256:c0add2c88039eefcf8f2d87a0cbbb24e275f2f9ec87f21883bc7c59ebe9bfe7a",
+  "gen_hash_zig": "sha256:f2074147e6c0cd2a5f32b68cd30e35375c2106f187d09ef55bbf0839c4d72d47",
   "module": "FpgaRcFilter",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-18T08:25:46Z",
+  "sealed_at": "2026-10-18T13:56:42Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
-  "spec_hash": "sha256:8fba8a419217ffe5dc6454759dd438d2236fb2cd829f9d64a3c2e15e3f44e51d",
+  "spec_hash": "sha256:be3af1aa6195d51e46289121cfd42623c80cd42d863442f4f6f69109da06d32f",
   "spec_path": "specs/fpga/rc_filter_ax7203.t27",
   "tests": {
     "failed": 0,

.trinity/seals/fpga_FpgaTern9mL0KWeights.json

@@ -0,0 +1,37 @@
+{
+  "built_by": "t27c-bootstrap@0.5.2+a86b691b1",
+  "closure": [
+    {
+      "spec": "specs/fpga/board_receipt.t27",
+      "spec_hash": "sha256:34634f7251ed8b2a1539748dd9aa8dbdb263d7c039e8635d05eea70c7857ceb2"
+    },
+    {
+      "spec": "specs/fpga/ddr3_ternary_matvec.t27",
+      "spec_hash": "sha256:84b7de73ff2f1a8679ca83443e0dcb62c5f30677cebc3015850331811420c16a"
+    }
+  ],
+  "config": "gen=c,rust,verilog,zig;tests=zig",
+  "gen_hash_c": "sha256:a1bc05c9dccc86398a7bc9f41cf8edc93c9545f35bf5be41dc38145327700c14",
+  "gen_hash_rust": "sha256:0f6232f05dbc51ad22947799c8ca0fab06c154afd4f572e80f46b55c4064f2b2",
+  "gen_hash_verilog": "sha256:43a2a07865e9a34ed7405f4a487e4c22c20d112abd9a74dbfe2da46cab3e8127",
+  "gen_hash_zig": "sha256:bd77315dd9e6410157ceaa8c59b5906e594814abcff5fce7b859a674597c871e",
+  "module": "FpgaTern9mL0KWeights",
+  "ring": 12,
+  "seal_schema": 2,
+  "sealed_at": "2026-10-18T16:39:57Z",
+  "sealed_by": "t27c-bootstrap@0.5.2",
+  "spec_hash": "sha256:43ee35ce1e0d1810b33cabe7517d109e4e469199fce38f4f563c5b5cceb9f448",
+  "spec_path": "specs/fpga/tern9m_l0_k_weights.t27",
+  "tests": {
+    "failed": 0,
+    "failing": [],
+    "forced": false,
+    "passed": 5,
+    "total": 5,
+    "vacuous": 0
+  },
+  "toolchain": {
+    "test_runner": "sha256:1982ae948e24d00c5d221ccec12dfce1eb01204b53e37b0f857f93b16d64629d",
+    "zig": "0.16.0"
+  }
+}

.trinity/seals/igla_own_model.json

@@ -1,5 +1,5 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+9448ab4be",
+  "built_by": "t27c-bootstrap@0.5.2+9e8ff7af6",
   "closure": [
     {
       "spec": "specs/t27f/reel.t27",
@@ -15,16 +15,16 @@
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
-  "gen_hash_c": "sha256:34f442903c5b74b1ddc28b310d9782b0f61c45098e4ff931771176583341057d",
-  "gen_hash_rust": "sha256:a0e037fe6d5dd9b82586a2bf2a80c27ff50f6c9ba7b9babe60e9b52349efaa5c",
-  "gen_hash_verilog": "sha256:64cba74ad08af9252262494d75e1ec94d598f81d5fa4b06bc3bff797d5ca5ad8",
-  "gen_hash_zig": "sha256:a180869d634e33aeca7c64cde565c2115d43ded528f7613a9ce9ad084ab787be",
+  "gen_hash_c": "sha256:5c6365f8b63c2904bb3b13278b99d66c84ade2025cf6ee084cb4cf19598c4c38",
+  "gen_hash_rust": "sha256:313643b2f632168a470d4d77396ca4da7bd110a32a0b51f2c3a96cb6030fbf06",
+  "gen_hash_verilog": "sha256:d2ac3cfcc384a8d8f14d55346b2d193670f4ad1424173ff7a5f524b5ecd69c5f",
+  "gen_hash_zig": "sha256:034324eec283aebddf41d64127dac4b6cdd871ce0ff1cb1c91ab17b58d8ffc69",
   "module": "own_model",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-18T17:03:43Z",
+  "sealed_at": "2026-10-18T22:16:17Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
-  "spec_hash": "sha256:2c3daec9e62ce9123e19cad921e57af75beb25a1870c234230ae5505a7d7ac79",
+  "spec_hash": "sha256:5a3d744947dc65b8c13d02a3ad58aa6c97f694f5459634110823788381a5ff80",
   "spec_path": "specs/igla/own_model.t27",
   "tests": {
     "failed": 0,
@@ -35,7 +35,7 @@
     "vacuous": 0
   },
   "toolchain": {
-    "test_runner": "sha256:1982ae948e24d00c5d221ccec12dfce1eb01204b53e37b0f857f93b16d64629d",
+    "test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
     "zig": "0.16.0"
   }
 }

.trinity/seals/igla_own_model_board.json

@@ -1,9 +1,9 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+9448ab4be",
+  "built_by": "t27c-bootstrap@0.5.2+9e8ff7af6",
   "closure": [
     {
       "spec": "specs/igla/own_model.t27",
-      "spec_hash": "sha256:2c3daec9e62ce9123e19cad921e57af75beb25a1870c234230ae5505a7d7ac79"
+      "spec_hash": "sha256:5a3d744947dc65b8c13d02a3ad58aa6c97f694f5459634110823788381a5ff80"
     },
     {
       "spec": "specs/t27f/reel.t27",
@@ -19,16 +19,16 @@
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
-  "gen_hash_c": "sha256:a0125cda52bdb9a87de3b170cc991ad71fc627caf8c60e4bc41a2f4a9a3a86e8",
-  "gen_hash_rust": "sha256:dc61033d126c3f954f8b6ae3f33c33f773edd8f5eda07530cf3576e56d39dd73",
-  "gen_hash_verilog": "sha256:0d56c85728676e996f03f9636d7492c02c2901cd034348565c28a657aa86731f",
-  "gen_hash_zig": "sha256:c742951d611cb908f642a7262478d7219717d0b3b3284c123aebd0d4cd63bff5",
+  "gen_hash_c": "sha256:e4afa57dd33fdae88c9bc8bcbad343ceadac9bb8ef19a775415b1d4582778f03",
+  "gen_hash_rust": "sha256:382521e2dadd256ffb9713a2fad1fc39f4fdd07fa18443c080cb186512b8aa65",
+  "gen_hash_verilog": "sha256:4e773a0e4aa1439990eeacc896f6b4d0ca8a43df1a92db6ffa69bb4d84d98655",
+  "gen_hash_zig": "sha256:270159ce45d856052de63181768a5f8f3af5f69180fa2ad917c5b5beff4ffa75",
   "module": "own_model_board",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-18T17:03:43Z",
+  "sealed_at": "2026-10-18T22:16:20Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
-  "spec_hash": "sha256:69e4e67d00d0a17aed8d5e9ed45d7c745c970d069388db37f7835ff39179adae",
+  "spec_hash": "sha256:dabe2457877296de9097c66834d3a29ad66aa1862cc86fc8242ae9ab1acd39e5",
   "spec_path": "specs/igla/own_model_board.t27",
   "tests": {
     "failed": 0,
@@ -39,7 +39,7 @@
     "vacuous": 0
   },
   "toolchain": {
-    "test_runner": "sha256:1982ae948e24d00c5d221ccec12dfce1eb01204b53e37b0f857f93b16d64629d",
+    "test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
     "zig": "0.16.0"
   }
 }

docs/reports/t27b_expectations.json

@@ -339,6 +339,7 @@
   {"path": "specs/fpga/apb_bridge.t27", "t27b": "pass"},
   {"path": "specs/fpga/assembler.t27", "t27b": "pass"},
   {"path": "specs/fpga/axi4.t27", "t27b": "pass"},
+  {"path": "specs/fpga/board_receipt.t27", "t27b": "pass"},
   {"path": "specs/fpga/boards/arty_a7_integration.t27", "t27b": "pass"},
   {"path": "specs/fpga/boards/qmtech_a100t_integration.t27", "t27b": "pass"},
   {"path": "specs/fpga/bootrom.t27", "t27b": "pass"},
@@ -348,6 +349,7 @@
   {"path": "specs/fpga/crossopt.t27", "t27b": "pass"},
   {"path": "specs/fpga/cts.t27", "t27b": "pass"},
   {"path": "specs/fpga/ddr3_head_bandwidth.t27", "t27b": "pass"},
+  {"path": "specs/fpga/ddr3_ternary_matvec.t27", "t27b": "pass"},
   {"path": "specs/fpga/dft.t27", "t27b": "pass"},
   {"path": "specs/fpga/die_probe.t27", "t27b": "pass"},
   {"path": "specs/fpga/dsp/adders.t27", "t27b": "pass"},
@@ -381,6 +383,7 @@
   {"path": "specs/fpga/simulator.t27", "t27b": "pass"},
   {"path": "specs/fpga/stdlib.t27", "t27b": "pass"},
   {"path": "specs/fpga/systolic.t27", "t27b": "pass"},
+  {"path": "specs/fpga/tern9m_l0_k_weights.t27", "t27b": "pass"},
   {"path": "specs/fpga/ternary_isa.t27", "t27b": "pass"},
   {"path": "specs/fpga/ternary_link.t27", "t27b": "pass"},
   {"path": "specs/fpga/testbench/assembler_tb.t27", "t27b": "pass"},

gen/json/igla/own_model_board.json

@@ -1 +1 @@
-{"job":"own_model","stage":"own_model","msg":"4 published, 22 verified, 1 drafts, 0 gaps; 62%","progress":0.62,"metrics":{"lens_pct":[68,70,48],"cells":[{"status":4,"pct":60},{"status":4,"pct":70},{"status":4,"pct":80},{"status":4,"pct":80},{"status":4,"pct":60},{"status":4,"pct":100},{"status":5,"pct":50},{"status":5,"pct":90},{"status":5,"pct":30},{"status":4,"pct":100},{"status":4,"pct":100},{"status":4,"pct":20},{"status":4,"pct":80},{"status":4,"pct":65},{"status":4,"pct":95},{"status":4,"pct":75},{"status":4,"pct":55},{"status":4,"pct":40},{"status":4,"pct":70},{"status":4,"pct":15},{"status":5,"pct":60},{"status":4,"pct":40},{"status":4,"pct":100},{"status":4,"pct":60},{"status":4,"pct":30},{"status":3,"pct":10},{"status":4,"pct":50}]}}
+{"job":"own_model","stage":"own_model","msg":"4 published, 23 verified, 0 drafts, 0 gaps; 62%","progress":0.62,"metrics":{"lens_pct":[68,70,48],"cells":[{"status":4,"pct":60},{"status":4,"pct":70},{"status":4,"pct":80},{"status":4,"pct":80},{"status":4,"pct":60},{"status":4,"pct":100},{"status":5,"pct":50},{"status":5,"pct":90},{"status":5,"pct":30},{"status":4,"pct":100},{"status":4,"pct":100},{"status":4,"pct":20},{"status":4,"pct":80},{"status":4,"pct":65},{"status":4,"pct":95},{"status":4,"pct":75},{"status":4,"pct":55},{"status":4,"pct":40},{"status":4,"pct":70},{"status":4,"pct":15},{"status":5,"pct":60},{"status":4,"pct":40},{"status":4,"pct":100},{"status":4,"pct":60},{"status":4,"pct":30},{"status":4,"pct":15},{"status":4,"pct":50}]}}

specs/fpga/board_receipt.t27

@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: Apache-2.0
+; specs/fpga/board_receipt.t27 -- the pieces of a board's UART receipt that every AX7203 board spec shares
+; The board specs specs/fpga/rc_filter_ax7203.t27, specs/fpga/ddr3_head_bandwidth.t27 and
+; specs/fpga/ddr3_ternary_matvec.t27 each print one receipt line on the UART; the two DDR3 ones also fold
+; 256-bit beats into a checksum. These are the bodies they had each written for themselves
+; (tools/dupe_scan.py): one home, used by each.
+; -
+; Pure functions only: no pins, no `pub var`, no on_clock, and no name a board spec also defines, so a `use`
+; of this module adds nothing to a board's netlist but the functions it calls (`t27b verilog` emits them
+; after the board's own; checked against the netlists from before the move).
+; A verdict of 0 is PASS in every board spec (each one's V_PASS); any other verdict that reaches
+; pass_fail_char prints FAIL. ddr3_head_bandwidth's SLOW and KILL lines keep their own verdict_char.
+; ASCII only, English only.
+; phi^2 + 1/phi^2 = 3 | TRINITY
+
+module FpgaBoardReceipt;
+
+/// The checksum after one more 256-bit beat: rotate the sum left by one, then xor in the four lanes, lane
+/// k rotated left by 16 * k.
+pub fn fold(sum: u64, l0: u64, l1: u64, l2: u64, l3: u64) -> u64 {
+    return ((sum << 1) | (sum >> 63)) ^ l0 ^ ((l1 << 16) | (l1 >> 48)) ^ ((l2 << 32) | (l2 >> 32)) ^ ((l3 << 48) | (l3 >> 16));
+}
+
+/// The ASCII digit of a nibble, 0-9 A-F.
+pub fn hex_digit(n: u8) -> u8 {
+    if ((n & 15) < 10) { return 48 + (n & 15); }
+    return 55 + (n & 15);
+}
+
+/// Character p of " PASS\r\n" (verdict 0) or " FAIL\r\n" (any other verdict).
+pub fn pass_fail_char(v: u8, p: u8) -> u8 {
+    if (p == 0) { return 32; }
+    if (p == 5) { return 13; }
+    if (p == 6) { return 10; }
+    if (v == 0) {
+        if (p == 1) { return 80; }
+        if (p == 2) { return 65; }
+        return 83;
+    }
+    if (p == 1) { return 70; }
+    if (p == 2) { return 65; }
+    if (p == 3) { return 73; }
+    return 76;
+}
+
+test hex_digit_covers_all_sixteen_nibbles_and_ignores_the_high_ones {
+    assert_eq(hex_digit(0), 48);
+    assert_eq(hex_digit(9), 57);
+    assert_eq(hex_digit(10), 65);
+    assert_eq(hex_digit(15), 70);
+    assert_eq(hex_digit(0xA7), 55);
+}
+
+test pass_fail_char_spells_pass_and_fail {
+    assert_eq(pass_fail_char(0, 0), 32);
+    assert_eq(pass_fail_char(0, 1), 80);
+    assert_eq(pass_fail_char(0, 2), 65);
+    assert_eq(pass_fail_char(0, 3), 83);
+    assert_eq(pass_fail_char(0, 4), 83);
+    assert_eq(pass_fail_char(0, 5), 13);
+    assert_eq(pass_fail_char(0, 6), 10);
+    assert_eq(pass_fail_char(3, 1), 70);
+    assert_eq(pass_fail_char(3, 2), 65);
+    assert_eq(pass_fail_char(3, 3), 73);
+    assert_eq(pass_fail_char(3, 4), 76);
+    assert_eq(pass_fail_char(1, 1), 70);
+}
+
+test fold_rotates_the_sum_and_each_lane {
+    assert_eq(fold(0, 0, 0, 0, 0), 0);
+    assert_eq(fold(1, 0, 0, 0, 0), 2);
+    assert_eq(fold(0x8000000000000000, 0, 0, 0, 0), 1);
+    assert_eq(fold(0, 1, 0, 0, 0), 1);
+    assert_eq(fold(0, 0, 1, 0, 0), 0x10000);
+    assert_eq(fold(0, 0, 0, 1, 0), 0x100000000);
+    assert_eq(fold(0, 0, 0, 0, 1), 0x1000000000000);
+    assert_eq(fold(0, 0, 0x8000000000000000, 0, 0), 0x8000);
+}
+
+test a_fold_that_dropped_a_lane_would_be_seen {
+    const a : u64 = fold(0x0123456789ABCDEF, 0x1111, 0x2222, 0x3333, 0x4444);
+    const b : u64 = fold(0x0123456789ABCDEF, 0x1111, 0x2222, 0x3333, 0);
+    assert(a != b);
+}