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docs(analog): competitors, prior art and ten weaknesses of the analog-emulation approach (Closes #10502) - #10506
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…-emulation approach (Closes #10502) Typhoon HIL, OPAL-RT eHS, Plexim, dSPACE, RTDS, NI, Simscape HDL, RNM, Stanford msdsl/svreal/anasymod, SPICE-on-FPGA papers, ngspice, Xyce, OpenVAF, cpphdl; where #10486 is not novel and where it may differ; weaknesses W1-W10, each with a mitigation and a measurable check. Every claim is tagged [V]/[S]/[U]/[I] with its URL. Thresholds are proposals. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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October 18, 2026 15:35
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Closes #10502
docs/analog/competitors.md(420 lines, ASCII, 83 lines with source URLs): commercial FPGA circuit solvers (Typhoon HIL, OPAL-RT eHS, Plexim RT Box, dSPACE, RTDS, NI), Simscape HDL, real-number modeling, Stanford msdsl/svreal/anasymod, academic SPICE-on-FPGA work, ngspice/XSPICE, Xyce, OpenVAF, cpphdl analog, AI-native analog tools.Findings that change the plan of #10486:
Every claim is tagged [V] read, [S] snippet, [U] unknown, [I] inference; proposed thresholds need the owner's sign-off before they become gates.
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