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fpga(ax7203): RLC and 5-node ladder through the linear cell -- one board top for both circuits, PASS on the board, negative controls FAIL on their own circuit (Closes #10565) #10578

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Merged
gHashTag merged 3 commits into from
Oct 19, 2026
Merged

fpga(ax7203): RLC and 5-node ladder through the linear cell -- one board top for both circuits, PASS on the board, negative controls FAIL on their own circuit (Closes #10565) #10578

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1b8d4f1
fpga(ax7203): RLC and 5-node ladder through the linear cell -- one bo…
claude Oct 18, 2026
ea35d9b
Merge branch 'master' into claude/analog-m1b-board-10496
gHashTag Oct 19, 2026
b773546
fpga: board_receipt's beat checksum is fold_beat, so the analog cell'…
claude Oct 19, 2026
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37 changes: 37 additions & 0 deletions .trinity/seals/fpga_FpgaAnalogCell.json
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@@ -0,0 +1,37 @@
{
"built_by": "t27c-bootstrap@0.5.2+ea35d9b72",
"closure": [
{
"spec": "specs/analog/linear.t27",
"spec_hash": "sha256:3ddef7be183aba583ed285334ee389b48a65b41335e98914514235db7c4e5d62"
},
{
"spec": "specs/fpga/rc_filter_ax7203.t27",
"spec_hash": "sha256:be3af1aa6195d51e46289121cfd42623c80cd42d863442f4f6f69109da06d32f"
}
],
"config": "gen=c,rust,verilog,zig;tests=zig",
"gen_hash_c": "sha256:82720a752019f679089c83012da03469a33e1d926aed3c1fb8834d85d048f8c7",
"gen_hash_rust": "sha256:58585b41c1243f7a1a80c46f0540f896a00bc282f029573adec866764824c579",
"gen_hash_verilog": "sha256:400e4cd5b90ca51eb4187847ad5912de497365f8e2ed5b75ed9124aec7dc0a73",
"gen_hash_zig": "sha256:1a1ab13f972fe545a593ab4c866076c0fb4220bb72075bf266644c4eb82833b3",
"module": "FpgaAnalogCell",
"ring": 12,
"seal_schema": 2,
"sealed_at": "2026-10-19T01:11:30Z",
"sealed_by": "t27c-bootstrap@0.5.2",
"spec_hash": "sha256:9980520c7b863914ad4962b8f3841cb1729d00a0c88b02ae4831b2877ab2b652",
"spec_path": "specs/fpga/analog_cell_ax7203.t27",
"tests": {
"failed": 0,
"failing": [],
"forced": false,
"passed": 11,
"total": 11,
"vacuous": 0
},
"toolchain": {
"test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
"zig": "0.16.0"
}
}
16 changes: 8 additions & 8 deletions .trinity/seals/fpga_FpgaBoardReceipt.json
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@@ -1,17 +1,17 @@
{
"built_by": "t27c-bootstrap@0.5.2+a86b691b1",
"built_by": "t27c-bootstrap@0.5.2+ea35d9b72",
"closure": [],
"config": "gen=c,rust,verilog,zig;tests=zig",
"gen_hash_c": "sha256:a5d6d0e10fdc5fa09a780007cd144fc129cf4de77c7762a9212bf64240806f34",
"gen_hash_rust": "sha256:f2efc42ebb64bbf2210158576b10c0fc652339aab5e1dcadac5cfda11472d192",
"gen_hash_verilog": "sha256:173a361ae8759a6ba7228d792947d405fed05747a23a9fd76afc768a2cfc3c61",
"gen_hash_zig": "sha256:34f3ca54b36f64c4e2b122d50f3f6c506275a5cf895e2478fdb4f6b15478c4b7",
"gen_hash_c": "sha256:d139e6c20f6e0ec7b82695f7d2129db82a790ce33469bf1f4cad5b232dbe5e07",
"gen_hash_rust": "sha256:8f229651558403c6f383bf5821e3bdd69fb19e21584e31ba9f55b0c328ac9119",
"gen_hash_verilog": "sha256:8a67141169339e2c4532917bbd174e4503b114b7825e73bed7c62bf2564c4a97",
"gen_hash_zig": "sha256:ef4c8fc51db4c3d9430be665982556fce21adcd53243c847affb26419368a767",
"module": "FpgaBoardReceipt",
"ring": 12,
"seal_schema": 2,
"sealed_at": "2026-10-18T13:56:40Z",
"sealed_at": "2026-10-19T01:11:02Z",
"sealed_by": "t27c-bootstrap@0.5.2",
"spec_hash": "sha256:34634f7251ed8b2a1539748dd9aa8dbdb263d7c039e8635d05eea70c7857ceb2",
"spec_hash": "sha256:dad72ec0abe3b1020f0e9bff20027682d1d40d26f427965ad111fa2282a325a1",
"spec_path": "specs/fpga/board_receipt.t27",
"tests": {
"failed": 0,
Expand All @@ -22,7 +22,7 @@
"vacuous": 0
},
"toolchain": {
"test_runner": "sha256:1982ae948e24d00c5d221ccec12dfce1eb01204b53e37b0f857f93b16d64629d",
"test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
"zig": "0.16.0"
}
}
18 changes: 9 additions & 9 deletions .trinity/seals/fpga_FpgaDdr3HeadBandwidth.json
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@@ -1,22 +1,22 @@
{
"built_by": "t27c-bootstrap@0.5.2+a86b691b1",
"built_by": "t27c-bootstrap@0.5.2+ea35d9b72",
"closure": [
{
"spec": "specs/fpga/board_receipt.t27",
"spec_hash": "sha256:34634f7251ed8b2a1539748dd9aa8dbdb263d7c039e8635d05eea70c7857ceb2"
"spec_hash": "sha256:dad72ec0abe3b1020f0e9bff20027682d1d40d26f427965ad111fa2282a325a1"
}
],
"config": "gen=c,rust,verilog,zig;tests=zig",
"gen_hash_c": "sha256:1b37e08fd08dbbc0645a49bc82a0dcc499e209d26f5e5734ae39d130f920fe58",
"gen_hash_rust": "sha256:9543f6cb7a6e90c6af7602df2c0c5373f88ca949b74e90742fce80a42c0baa7e",
"gen_hash_verilog": "sha256:c8408e1ad2d20562e6f624647dca216e9d06483006eefeba1ce57857dd3fad09",
"gen_hash_zig": "sha256:ed9f25e68b8a6a456ec6eda990b40bc89a2abf948e8b87e46910eacb7b6830a3",
"gen_hash_c": "sha256:3248e16baecb5ee11a6d7fa26ae227b25cb59aaa5dc2cb7134c6f088258feadc",
"gen_hash_rust": "sha256:c0611521a3e92417d9001deff13337dfc67e076b653401e427c763eb60f0c3e9",
"gen_hash_verilog": "sha256:6136d87130ca4fd11fc8ecffd7d742a6de6c80ddd29ea9bc1055011861fff74c",
"gen_hash_zig": "sha256:cfac0b07859bec1b77fe08fde2f147c3882de0f2ecdf7698049e19b99577eeb5",
"module": "FpgaDdr3HeadBandwidth",
"ring": 12,
"seal_schema": 2,
"sealed_at": "2026-10-18T13:56:41Z",
"sealed_at": "2026-10-19T01:11:07Z",
"sealed_by": "t27c-bootstrap@0.5.2",
"spec_hash": "sha256:152bf98420d4c3919835eefdb3cad56c76cd80cbecc11e1bcb6616fc25dfdd04",
"spec_hash": "sha256:aec485ee482ee1833a3518087f6381d9f75bbd49854d01ef1dd09053a56c4c9e",
"spec_path": "specs/fpga/ddr3_head_bandwidth.t27",
"tests": {
"failed": 0,
Expand All @@ -27,7 +27,7 @@
"vacuous": 0
},
"toolchain": {
"test_runner": "sha256:1982ae948e24d00c5d221ccec12dfce1eb01204b53e37b0f857f93b16d64629d",
"test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
"zig": "0.16.0"
}
}
18 changes: 9 additions & 9 deletions .trinity/seals/fpga_FpgaDdr3TernaryMatvec.json
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@@ -1,22 +1,22 @@
{
"built_by": "t27c-bootstrap@0.5.2+a86b691b1",
"built_by": "t27c-bootstrap@0.5.2+ea35d9b72",
"closure": [
{
"spec": "specs/fpga/board_receipt.t27",
"spec_hash": "sha256:34634f7251ed8b2a1539748dd9aa8dbdb263d7c039e8635d05eea70c7857ceb2"
"spec_hash": "sha256:dad72ec0abe3b1020f0e9bff20027682d1d40d26f427965ad111fa2282a325a1"
}
],
"config": "gen=c,rust,verilog,zig;tests=zig",
"gen_hash_c": "sha256:af4d241ce9398f06df4527b2e7d8db1f81eeefa0c1298ec4be8840302236d92f",
"gen_hash_rust": "sha256:0f474fbf43039fa0da4932752897314fb70fddac664e0efbf3f98b535fae9895",
"gen_hash_verilog": "sha256:7dd8c000bec8d732ebf2538e289621bee1f3c1e751df53f583beaaddf349680a",
"gen_hash_zig": "sha256:d38c2a80429c2b66adc024d7723b227ccaf2f792259277196f3255ebd3cd0f44",
"gen_hash_c": "sha256:a342d03c59ede4a34c4bc0fa93285f1fd273eeb9a0cb3b13fd6ca1913848e2b3",
"gen_hash_rust": "sha256:c0d46dd557d195d583211fffe5c3c47e1ac32323d6e789688c80b416eaec8c6b",
"gen_hash_verilog": "sha256:0c149fb374f44339aa3d65c9c95f9bd1995c661186a28b34767fb6bf312c02d0",
"gen_hash_zig": "sha256:e54b2d4c607a3299647b51b831c36e0fd6935a80036a35c89206da1ef6261013",
"module": "FpgaDdr3TernaryMatvec",
"ring": 12,
"seal_schema": 2,
"sealed_at": "2026-10-18T15:37:16Z",
"sealed_at": "2026-10-19T01:11:09Z",
"sealed_by": "t27c-bootstrap@0.5.2",
"spec_hash": "sha256:84b7de73ff2f1a8679ca83443e0dcb62c5f30677cebc3015850331811420c16a",
"spec_hash": "sha256:09d56919a54d89a7636534eaea5290ed3fcfc31d0c5cef3ef069cad77ebc9d87",
"spec_path": "specs/fpga/ddr3_ternary_matvec.t27",
"tests": {
"failed": 0,
Expand All @@ -27,7 +27,7 @@
"vacuous": 0
},
"toolchain": {
"test_runner": "sha256:1982ae948e24d00c5d221ccec12dfce1eb01204b53e37b0f857f93b16d64629d",
"test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
"zig": "0.16.0"
}
}
8 changes: 4 additions & 4 deletions .trinity/seals/fpga_FpgaRcFilter.json
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@@ -1,9 +1,9 @@
{
"built_by": "t27c-bootstrap@0.5.2+a86b691b1",
"built_by": "t27c-bootstrap@0.5.2+ea35d9b72",
"closure": [
{
"spec": "specs/fpga/board_receipt.t27",
"spec_hash": "sha256:34634f7251ed8b2a1539748dd9aa8dbdb263d7c039e8635d05eea70c7857ceb2"
"spec_hash": "sha256:dad72ec0abe3b1020f0e9bff20027682d1d40d26f427965ad111fa2282a325a1"
}
],
"config": "gen=c,rust,verilog,zig;tests=zig",
Expand All @@ -14,7 +14,7 @@
"module": "FpgaRcFilter",
"ring": 12,
"seal_schema": 2,
"sealed_at": "2026-10-18T13:56:42Z",
"sealed_at": "2026-10-19T01:11:27Z",
"sealed_by": "t27c-bootstrap@0.5.2",
"spec_hash": "sha256:be3af1aa6195d51e46289121cfd42623c80cd42d863442f4f6f69109da06d32f",
"spec_path": "specs/fpga/rc_filter_ax7203.t27",
Expand All @@ -27,7 +27,7 @@
"vacuous": 0
},
"toolchain": {
"test_runner": "sha256:1982ae948e24d00c5d221ccec12dfce1eb01204b53e37b0f857f93b16d64629d",
"test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
"zig": "0.16.0"
}
}
20 changes: 10 additions & 10 deletions .trinity/seals/fpga_FpgaTern9mL0KWeights.json
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@@ -1,26 +1,26 @@
{
"built_by": "t27c-bootstrap@0.5.2+a86b691b1",
"built_by": "t27c-bootstrap@0.5.2+ea35d9b72",
"closure": [
{
"spec": "specs/fpga/board_receipt.t27",
"spec_hash": "sha256:34634f7251ed8b2a1539748dd9aa8dbdb263d7c039e8635d05eea70c7857ceb2"
"spec_hash": "sha256:dad72ec0abe3b1020f0e9bff20027682d1d40d26f427965ad111fa2282a325a1"
},
{
"spec": "specs/fpga/ddr3_ternary_matvec.t27",
"spec_hash": "sha256:84b7de73ff2f1a8679ca83443e0dcb62c5f30677cebc3015850331811420c16a"
"spec_hash": "sha256:09d56919a54d89a7636534eaea5290ed3fcfc31d0c5cef3ef069cad77ebc9d87"
}
],
"config": "gen=c,rust,verilog,zig;tests=zig",
"gen_hash_c": "sha256:a1bc05c9dccc86398a7bc9f41cf8edc93c9545f35bf5be41dc38145327700c14",
"gen_hash_rust": "sha256:0f6232f05dbc51ad22947799c8ca0fab06c154afd4f572e80f46b55c4064f2b2",
"gen_hash_verilog": "sha256:43a2a07865e9a34ed7405f4a487e4c22c20d112abd9a74dbfe2da46cab3e8127",
"gen_hash_zig": "sha256:bd77315dd9e6410157ceaa8c59b5906e594814abcff5fce7b859a674597c871e",
"gen_hash_c": "sha256:e17b6372fb0007de7ffeb5f73119e6e0ccb7b52a7e073e82428e68daef147f34",
"gen_hash_rust": "sha256:f65498c3aa02c6195e4a50ddbac6ee0dde40d1f81e8a14591bece9c4a05f1757",
"gen_hash_verilog": "sha256:03d2802eb117e8ce690afd09f636f0ec02764f18e741b4fcdaf2d3fa464987e9",
"gen_hash_zig": "sha256:6a00b49c743f944a6ba2ca04fae04ab21acafcbfb589a0dda3d8d22c4264c3e4",
"module": "FpgaTern9mL0KWeights",
"ring": 12,
"seal_schema": 2,
"sealed_at": "2026-10-18T16:39:57Z",
"sealed_at": "2026-10-19T01:11:04Z",
"sealed_by": "t27c-bootstrap@0.5.2",
"spec_hash": "sha256:43ee35ce1e0d1810b33cabe7517d109e4e469199fce38f4f563c5b5cceb9f448",
"spec_hash": "sha256:ea62f86f729a344db8f8a312854ca555d5eb6fce7408b0f1ff3ea9da5488f5b2",
"spec_path": "specs/fpga/tern9m_l0_k_weights.t27",
"tests": {
"failed": 0,
Expand All @@ -31,7 +31,7 @@
"vacuous": 0
},
"toolchain": {
"test_runner": "sha256:1982ae948e24d00c5d221ccec12dfce1eb01204b53e37b0f857f93b16d64629d",
"test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
"zig": "0.16.0"
}
}
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