t27f: deps view writes the use lines t27c does not resolve as unknown…

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Issue Gate on: pull_request_target 2

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PR budget (at most 20 open ready PRs per author; the excess waits as a draft) on: pull_request_target 3

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Seal Coverage on: pull_request 2

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Conflict Markers on: pull_request 2

Conflict markers (no unresolved merges)

Withdrawn Number Gate on: pull_request 2

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t27b native on: pull_request 5

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Duplicate Body Ratchet on: pull_request 1

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Fix Carries Source on: pull_request 1

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Gate Topology on: pull_request 4

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Spec Guards on: pull_request 11

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PHI Loop CI on: pull_request 1

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Documented Commands on: pull_request 2

Documented t27c subcommands exist

Harness scratch directories on: pull_request 2

No test binary shares one scratch directory

Verilog Widths on: pull_request 2

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Orphaned modules on: pull_request 2

Every source file is reachable from its crate root

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Emit Bit-Exact Gate (CI-02) on: pull_request 2

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t27f: deps view writes the use lines t27c does not resolve as unknown…

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