analog M4c: the SAR ADC bootstrapped sampling switch -- M4b's solver reused, square law against ngspice LEVEL=1 (Closes #10753)

.trinity/seals/analog_AnalogSarComparator.json

@@ -11,16 +11,16 @@
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
-  "gen_hash_c": "sha256:e6f3677d7f54078eabbdd3e3786cd6028cb0445eb4cf8f05b313a3d4ff618225",
-  "gen_hash_rust": "sha256:0b7f0fe869197f808776e207bceee2075fd591d253ced3f2ac9f6c6c6cd62f97",
-  "gen_hash_verilog": "sha256:bab3512235c19a5adbe9a9149e589999fc93bbac49484ff62864ed7dae37e140",
-  "gen_hash_zig": "sha256:ac367deed0470ab29568a4caa691a067ad8d341b9f6e5d356be531a026506510",
+  "gen_hash_c": "sha256:13f523685de5d6085818b938b8d9596938d50da2fbba1dae8b9978e50bfbd936",
+  "gen_hash_rust": "sha256:e58bde7196705be96ecd9c21fb54a3cbcea6323bd29a01f8abb46ee3b834b427",
+  "gen_hash_verilog": "sha256:b54771cd79b42bbba9ee294e993e3e096420931b1b2f832c3d00f46a28d5e8d8",
+  "gen_hash_zig": "sha256:21ae8f9401db2831f43303ca4b0f2b15ef9d3ed6cd00196b90bedb15ef15ed91",
   "module": "AnalogSarComparator",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-19T02:10:33Z",
+  "sealed_at": "2026-10-19T02:37:52Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
-  "spec_hash": "sha256:2df42ed0afe41add0b43762dfa05c8aa38ecbc022bea8f7bbd72f55917bcb806",
+  "spec_hash": "sha256:b88d05d5d17937024580ab40e80b698b63962cab531164d4a94a5dddd05a72a8",
   "spec_path": "specs/analog/sar_comparator.t27",
   "tests": {
     "failed": 0,

.trinity/seals/analog_AnalogSarSwitch.json

@@ -0,0 +1,45 @@
+{
+  "built_by": "t27c-bootstrap@0.5.2+ea35d9b72",
+  "closure": [
+    {
+      "spec": "specs/analog/linear.t27",
+      "spec_hash": "sha256:3ddef7be183aba583ed285334ee389b48a65b41335e98914514235db7c4e5d62"
+    },
+    {
+      "spec": "specs/analog/mos_table.t27",
+      "spec_hash": "sha256:9c0d1537ed5d8d60c4bdcb67d1e4c73ef80270e8cab224cb089c5b568fe11182"
+    },
+    {
+      "spec": "specs/analog/sar_cdac.t27",
+      "spec_hash": "sha256:0fa41f4de9f797a091d30fdf51896c81971b6d0504587431267172179a711309"
+    },
+    {
+      "spec": "specs/analog/sar_comparator.t27",
+      "spec_hash": "sha256:b88d05d5d17937024580ab40e80b698b63962cab531164d4a94a5dddd05a72a8"
+    }
+  ],
+  "config": "gen=c,rust,verilog,zig;tests=zig",
+  "gen_hash_c": "sha256:6e492ec2213718c6c5ff75ccb37596f928458a6a8060f2fc000207523bac2bb9",
+  "gen_hash_rust": "sha256:e8fb7bae8ce6f39a0b03e44d31689454e5f8bdbcfcd3827b323ec7b062ea6bb3",
+  "gen_hash_verilog": "sha256:f31945ee45a0caad66a141d1053dd9de2d67552dcd79f640014961ea8d1b24cc",
+  "gen_hash_zig": "sha256:4acac8aa8b54c017bf36f38aad67346a2d8abca7fdfe8c0dbf7d25f26f083aae",
+  "module": "AnalogSarSwitch",
+  "ring": 12,
+  "seal_schema": 2,
+  "sealed_at": "2026-10-19T02:37:55Z",
+  "sealed_by": "t27c-bootstrap@0.5.2",
+  "spec_hash": "sha256:122726502a51cb4c8980674b819ee3251bf8ee69a5586d6cd44a5eafcf284cb4",
+  "spec_path": "specs/analog/sar_switch.t27",
+  "tests": {
+    "failed": 0,
+    "failing": [],
+    "forced": false,
+    "passed": 14,
+    "total": 14,
+    "vacuous": 0
+  },
+  "toolchain": {
+    "test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
+    "zig": "0.16.0"
+  }
+}

specs/analog/decks/sar_sw_dc02.cir

@@ -0,0 +1,62 @@
+SAR ADC tracking switch, dc02: Vin = 0.2 V
+* specs/analog/decks/sar_sw_dc02.cir -- test data for specs/analog/sar_switch.t27 (#10753). A plain netlist, no .control block.
+* Circuit: the tracking_switch subcircuit of the uberWAVE golden SAR deck (wp2-parser/golden/top.spice; GPL-2.0, read at run time and never
+* vendored) -- ten transistors M1..M10 here for its XM1..XM10, with the W, L and m of that deck (n: 1u / 0.45u, p: 3u / 0.45u, m = 1) -- plus the
+* inverter x1 that makes nclk (the deck's n_clks) from clks (Mip, Min), the boost capacitor C3 between net2 and net4, and the 4 fF node capacitors.
+* M6 is the switch (Vout - Vin, gate net3); the boost capacitor lifts net3 about Vdd above Vin while clks is high. Square law: MOSFET LEVEL=1
+* (Shichman-Hodges), KP 300 uA/V^2 (n) and 100 uA/V^2 (p), VTO +-0.35 V, LAMBDA 0, GAMMA 0, and the bulk junctions off (IS = JS = CBD = CBS = 0);
+* no TOX, CGSO, CGDO, CGBO or CJ is set, so the only capacitance is the explicit one. This is the SQUARE LAW, not PSP103.
+* Capacitors: C3 (boost) = cap_cmim 20 um x 20 um = 603.2 fF: the IHP PDK at 21133f21 sets C = CJ L W + 2 CJSW (L + W) with CJ = 1.5e-15 and
+* CJSW = 40e-18 in units of m^2 and m (ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib:22 and capacitors_mod.lib:58,72), which is
+* 600 fF + 3.2 fF; its 55 mOhm series resistor is left out. Vout carries C2 = 4 fF plus the M4a DAC's top plate: 31.96875 units of the 9 um x 9 um
+* cap_cmim (122.94 fF) = 3930.2 fF, in all 3934.2 fF. net1, net2, net4, net5: 4 fF; net3: 8 fF (C6 and C8). nclk: 1 fF, which the deck does NOT have:
+* the square law has no gate capacitance, and a node with no capacitor and two devices in saturation has no Newton slope. Vdd 1.5 V.
+* Time: backward Euler on a fixed 250 ps grid. clks is the deck's PULSE(0 1.5 0 2n 2n 80n 500n) cut after one pulse: a rise of 8 steps (2 ns),
+* 320 steps at 1.5 V (the track phase), a fall of 8 steps, then 80 steps low (the hold), 416 steps in all; it is a B source in the grid index
+* nint(time/dt) - 10 (no breakpoint). Vin is the constant 0.2 V (nint(0.2 * 2^24) / 2^24, the spec's own word).
+* The circuit rests until clks moves: net1, net4, nclk at 1.5 V, net2, net3, net5 at 0, Vout 0.1 V (1677722 units of 2^-24 V) under Vin.
+* ngspice opens with a ramp of small steps and then takes 250 ps steps on the grid; 10 idle grid points come first, so step j of the spec is the row with
+* nint(time/dt) = j + 10 (time (j + 10) dt - 10 ps). Options: gear with maxord 1 is backward Euler; trtol 1e7 keeps the truncation test from shrinking a step;
+* reltol 1e-7, vntol 1e-10, abstol 1e-13 are the tightest at which ngspice still takes every step whole (tighter and its Newton splits the steps at the clock
+* edges, which is then not one backward Euler step); gmin 1e-18 so that no leak is added.
+* Measured (the .meas lines, 6 digits; the spec pins 10 digits read from `ngspice -b -r deck.raw`, a float64 raw file): od = V(net3) - V(Vin) at step 328, the gate
+* overdrive while tracking; te = V(Vout) - V(Vin) at step 328; vo_f, vo_h, vo_e = V(Vout) at steps 328, 344, 416: the injection step is vo_h - vo_f and the droop vo_e - vo_h.
+* Run: ngspice -b sar_sw_dc02.cir   (do not add -r: ngspice refuses .meas together with a raw file)
+.model nmos1 nmos level=1 vto=0.35 kp=300u lambda=0 gamma=0 is=0 js=0 cbd=0 cbs=0
+.model pmos1 pmos level=1 vto=-0.35 kp=100u lambda=0 is=0 js=0 cbd=0 cbs=0
+Vdd vdd 0 1.5
+Bclk clks 0 V = 1.5*min(max(min(min(nint(time/250p)-10,8),336-(nint(time/250p)-10)),0),8)/8
+Bvin vin 0 V = nint(0.2*16777216)/16777216
+M1 net1 clks vdd vdd pmos1 w=3u l=0.45u
+M2 net1 clks net2 0 nmos1 w=1u l=0.45u
+M3 net1 net3 net2 0 nmos1 w=1u l=0.45u
+M4 net2 nclk 0 0 nmos1 w=1u l=0.45u
+M5 vin net3 net2 0 nmos1 w=1u l=0.45u
+M6 vout net3 vin 0 nmos1 w=1u l=0.45u
+M7 vdd net3 net4 net4 pmos1 w=3u l=0.45u
+M8 net3 vdd net5 0 nmos1 w=1u l=0.45u
+M9 net5 nclk 0 0 nmos1 w=1u l=0.45u
+M10 net3 net1 net4 net4 pmos1 w=3u l=0.45u
+Mip nclk clks vdd vdd pmos1 w=3u l=0.45u
+Min nclk clks 0 0 nmos1 w=1u l=0.45u
+C3 net2 net4 603.2f
+C1 net4 0 4f
+C2 vout 0 3934.2f
+C4 net1 0 4f
+C6 net3 0 4f
+C8 net3 0 4f
+C7 net5 0 4f
+C5 net2 0 4f
+Cnc nclk 0 1f
+Bod od 0 V = v(net3)-v(vin)
+Bte te 0 V = v(vout)-v(vin)
+.ic v(net1)=1.5 v(net2)=0 v(net3)=0 v(net4)=1.5 v(net5)=0 v(nclk)=1.5 v(vout)=0.09999996423721313
+.options method=gear maxord=1 trtol=1e7 reltol=1e-7 vntol=1e-10 abstol=1e-13 gmin=1e-18 itl4=500
+.tran 250p 106.625n 0 250p uic
+.meas tran od find v(od) at=84.5n
+.meas tran te find v(te) at=84.5n
+.meas tran vo_f find v(vout) at=84.5n
+.meas tran vo_h find v(vout) at=88.5n
+.meas tran vo_e find v(vout) at=106.5n
+.print tran v(vout) v(net1) v(net2) v(net3) v(net4) v(net5) v(nclk) v(od) v(te)
+.end

specs/analog/decks/sar_sw_dc075.cir

@@ -0,0 +1,62 @@
+SAR ADC tracking switch, dc075: Vin = 0.75 V
+* specs/analog/decks/sar_sw_dc075.cir -- test data for specs/analog/sar_switch.t27 (#10753). A plain netlist, no .control block.
+* Circuit: the tracking_switch subcircuit of the uberWAVE golden SAR deck (wp2-parser/golden/top.spice; GPL-2.0, read at run time and never
+* vendored) -- ten transistors M1..M10 here for its XM1..XM10, with the W, L and m of that deck (n: 1u / 0.45u, p: 3u / 0.45u, m = 1) -- plus the
+* inverter x1 that makes nclk (the deck's n_clks) from clks (Mip, Min), the boost capacitor C3 between net2 and net4, and the 4 fF node capacitors.
+* M6 is the switch (Vout - Vin, gate net3); the boost capacitor lifts net3 about Vdd above Vin while clks is high. Square law: MOSFET LEVEL=1
+* (Shichman-Hodges), KP 300 uA/V^2 (n) and 100 uA/V^2 (p), VTO +-0.35 V, LAMBDA 0, GAMMA 0, and the bulk junctions off (IS = JS = CBD = CBS = 0);
+* no TOX, CGSO, CGDO, CGBO or CJ is set, so the only capacitance is the explicit one. This is the SQUARE LAW, not PSP103.
+* Capacitors: C3 (boost) = cap_cmim 20 um x 20 um = 603.2 fF: the IHP PDK at 21133f21 sets C = CJ L W + 2 CJSW (L + W) with CJ = 1.5e-15 and
+* CJSW = 40e-18 in units of m^2 and m (ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib:22 and capacitors_mod.lib:58,72), which is
+* 600 fF + 3.2 fF; its 55 mOhm series resistor is left out. Vout carries C2 = 4 fF plus the M4a DAC's top plate: 31.96875 units of the 9 um x 9 um
+* cap_cmim (122.94 fF) = 3930.2 fF, in all 3934.2 fF. net1, net2, net4, net5: 4 fF; net3: 8 fF (C6 and C8). nclk: 1 fF, which the deck does NOT have:
+* the square law has no gate capacitance, and a node with no capacitor and two devices in saturation has no Newton slope. Vdd 1.5 V.
+* Time: backward Euler on a fixed 250 ps grid. clks is the deck's PULSE(0 1.5 0 2n 2n 80n 500n) cut after one pulse: a rise of 8 steps (2 ns),
+* 320 steps at 1.5 V (the track phase), a fall of 8 steps, then 80 steps low (the hold), 416 steps in all; it is a B source in the grid index
+* nint(time/dt) - 10 (no breakpoint). Vin is the constant 0.75 V (nint(0.75 * 2^24) / 2^24, the spec's own word).
+* The circuit rests until clks moves: net1, net4, nclk at 1.5 V, net2, net3, net5 at 0, Vout 0.1 V (1677722 units of 2^-24 V) under Vin.
+* ngspice opens with a ramp of small steps and then takes 250 ps steps on the grid; 10 idle grid points come first, so step j of the spec is the row with
+* nint(time/dt) = j + 10 (time (j + 10) dt - 10 ps). Options: gear with maxord 1 is backward Euler; trtol 1e7 keeps the truncation test from shrinking a step;
+* reltol 1e-7, vntol 1e-10, abstol 1e-13 are the tightest at which ngspice still takes every step whole (tighter and its Newton splits the steps at the clock
+* edges, which is then not one backward Euler step); gmin 1e-18 so that no leak is added.
+* Measured (the .meas lines, 6 digits; the spec pins 10 digits read from `ngspice -b -r deck.raw`, a float64 raw file): od = V(net3) - V(Vin) at step 328, the gate
+* overdrive while tracking; te = V(Vout) - V(Vin) at step 328; vo_f, vo_h, vo_e = V(Vout) at steps 328, 344, 416: the injection step is vo_h - vo_f and the droop vo_e - vo_h.
+* Run: ngspice -b sar_sw_dc075.cir   (do not add -r: ngspice refuses .meas together with a raw file)
+.model nmos1 nmos level=1 vto=0.35 kp=300u lambda=0 gamma=0 is=0 js=0 cbd=0 cbs=0
+.model pmos1 pmos level=1 vto=-0.35 kp=100u lambda=0 is=0 js=0 cbd=0 cbs=0
+Vdd vdd 0 1.5
+Bclk clks 0 V = 1.5*min(max(min(min(nint(time/250p)-10,8),336-(nint(time/250p)-10)),0),8)/8
+Bvin vin 0 V = nint(0.75*16777216)/16777216
+M1 net1 clks vdd vdd pmos1 w=3u l=0.45u
+M2 net1 clks net2 0 nmos1 w=1u l=0.45u
+M3 net1 net3 net2 0 nmos1 w=1u l=0.45u
+M4 net2 nclk 0 0 nmos1 w=1u l=0.45u
+M5 vin net3 net2 0 nmos1 w=1u l=0.45u
+M6 vout net3 vin 0 nmos1 w=1u l=0.45u
+M7 vdd net3 net4 net4 pmos1 w=3u l=0.45u
+M8 net3 vdd net5 0 nmos1 w=1u l=0.45u
+M9 net5 nclk 0 0 nmos1 w=1u l=0.45u
+M10 net3 net1 net4 net4 pmos1 w=3u l=0.45u
+Mip nclk clks vdd vdd pmos1 w=3u l=0.45u
+Min nclk clks 0 0 nmos1 w=1u l=0.45u
+C3 net2 net4 603.2f
+C1 net4 0 4f
+C2 vout 0 3934.2f
+C4 net1 0 4f
+C6 net3 0 4f
+C8 net3 0 4f
+C7 net5 0 4f
+C5 net2 0 4f
+Cnc nclk 0 1f
+Bod od 0 V = v(net3)-v(vin)
+Bte te 0 V = v(vout)-v(vin)
+.ic v(net1)=1.5 v(net2)=0 v(net3)=0 v(net4)=1.5 v(net5)=0 v(nclk)=1.5 v(vout)=0.6499999761581421
+.options method=gear maxord=1 trtol=1e7 reltol=1e-7 vntol=1e-10 abstol=1e-13 gmin=1e-18 itl4=500
+.tran 250p 106.625n 0 250p uic
+.meas tran od find v(od) at=84.5n
+.meas tran te find v(te) at=84.5n
+.meas tran vo_f find v(vout) at=84.5n
+.meas tran vo_h find v(vout) at=88.5n
+.meas tran vo_e find v(vout) at=106.5n
+.print tran v(vout) v(net1) v(net2) v(net3) v(net4) v(net5) v(nclk) v(od) v(te)
+.end

specs/analog/decks/sar_sw_dc13.cir

@@ -0,0 +1,62 @@
+SAR ADC tracking switch, dc13: Vin = 1.3 V
+* specs/analog/decks/sar_sw_dc13.cir -- test data for specs/analog/sar_switch.t27 (#10753). A plain netlist, no .control block.
+* Circuit: the tracking_switch subcircuit of the uberWAVE golden SAR deck (wp2-parser/golden/top.spice; GPL-2.0, read at run time and never
+* vendored) -- ten transistors M1..M10 here for its XM1..XM10, with the W, L and m of that deck (n: 1u / 0.45u, p: 3u / 0.45u, m = 1) -- plus the
+* inverter x1 that makes nclk (the deck's n_clks) from clks (Mip, Min), the boost capacitor C3 between net2 and net4, and the 4 fF node capacitors.
+* M6 is the switch (Vout - Vin, gate net3); the boost capacitor lifts net3 about Vdd above Vin while clks is high. Square law: MOSFET LEVEL=1
+* (Shichman-Hodges), KP 300 uA/V^2 (n) and 100 uA/V^2 (p), VTO +-0.35 V, LAMBDA 0, GAMMA 0, and the bulk junctions off (IS = JS = CBD = CBS = 0);
+* no TOX, CGSO, CGDO, CGBO or CJ is set, so the only capacitance is the explicit one. This is the SQUARE LAW, not PSP103.
+* Capacitors: C3 (boost) = cap_cmim 20 um x 20 um = 603.2 fF: the IHP PDK at 21133f21 sets C = CJ L W + 2 CJSW (L + W) with CJ = 1.5e-15 and
+* CJSW = 40e-18 in units of m^2 and m (ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib:22 and capacitors_mod.lib:58,72), which is
+* 600 fF + 3.2 fF; its 55 mOhm series resistor is left out. Vout carries C2 = 4 fF plus the M4a DAC's top plate: 31.96875 units of the 9 um x 9 um
+* cap_cmim (122.94 fF) = 3930.2 fF, in all 3934.2 fF. net1, net2, net4, net5: 4 fF; net3: 8 fF (C6 and C8). nclk: 1 fF, which the deck does NOT have:
+* the square law has no gate capacitance, and a node with no capacitor and two devices in saturation has no Newton slope. Vdd 1.5 V.
+* Time: backward Euler on a fixed 250 ps grid. clks is the deck's PULSE(0 1.5 0 2n 2n 80n 500n) cut after one pulse: a rise of 8 steps (2 ns),
+* 320 steps at 1.5 V (the track phase), a fall of 8 steps, then 80 steps low (the hold), 416 steps in all; it is a B source in the grid index
+* nint(time/dt) - 10 (no breakpoint). Vin is the constant 1.3 V (nint(1.3 * 2^24) / 2^24, the spec's own word).
+* The circuit rests until clks moves: net1, net4, nclk at 1.5 V, net2, net3, net5 at 0, Vout 0.1 V (1677722 units of 2^-24 V) under Vin.
+* ngspice opens with a ramp of small steps and then takes 250 ps steps on the grid; 10 idle grid points come first, so step j of the spec is the row with
+* nint(time/dt) = j + 10 (time (j + 10) dt - 10 ps). Options: gear with maxord 1 is backward Euler; trtol 1e7 keeps the truncation test from shrinking a step;
+* reltol 1e-7, vntol 1e-10, abstol 1e-13 are the tightest at which ngspice still takes every step whole (tighter and its Newton splits the steps at the clock
+* edges, which is then not one backward Euler step); gmin 1e-18 so that no leak is added.
+* Measured (the .meas lines, 6 digits; the spec pins 10 digits read from `ngspice -b -r deck.raw`, a float64 raw file): od = V(net3) - V(Vin) at step 328, the gate
+* overdrive while tracking; te = V(Vout) - V(Vin) at step 328; vo_f, vo_h, vo_e = V(Vout) at steps 328, 344, 416: the injection step is vo_h - vo_f and the droop vo_e - vo_h.
+* Run: ngspice -b sar_sw_dc13.cir   (do not add -r: ngspice refuses .meas together with a raw file)
+.model nmos1 nmos level=1 vto=0.35 kp=300u lambda=0 gamma=0 is=0 js=0 cbd=0 cbs=0
+.model pmos1 pmos level=1 vto=-0.35 kp=100u lambda=0 is=0 js=0 cbd=0 cbs=0
+Vdd vdd 0 1.5
+Bclk clks 0 V = 1.5*min(max(min(min(nint(time/250p)-10,8),336-(nint(time/250p)-10)),0),8)/8
+Bvin vin 0 V = nint(1.3*16777216)/16777216
+M1 net1 clks vdd vdd pmos1 w=3u l=0.45u
+M2 net1 clks net2 0 nmos1 w=1u l=0.45u
+M3 net1 net3 net2 0 nmos1 w=1u l=0.45u
+M4 net2 nclk 0 0 nmos1 w=1u l=0.45u
+M5 vin net3 net2 0 nmos1 w=1u l=0.45u
+M6 vout net3 vin 0 nmos1 w=1u l=0.45u
+M7 vdd net3 net4 net4 pmos1 w=3u l=0.45u
+M8 net3 vdd net5 0 nmos1 w=1u l=0.45u
+M9 net5 nclk 0 0 nmos1 w=1u l=0.45u
+M10 net3 net1 net4 net4 pmos1 w=3u l=0.45u
+Mip nclk clks vdd vdd pmos1 w=3u l=0.45u
+Min nclk clks 0 0 nmos1 w=1u l=0.45u
+C3 net2 net4 603.2f
+C1 net4 0 4f
+C2 vout 0 3934.2f
+C4 net1 0 4f
+C6 net3 0 4f
+C8 net3 0 4f
+C7 net5 0 4f
+C5 net2 0 4f
+Cnc nclk 0 1f
+Bod od 0 V = v(net3)-v(vin)
+Bte te 0 V = v(vout)-v(vin)
+.ic v(net1)=1.5 v(net2)=0 v(net3)=0 v(net4)=1.5 v(net5)=0 v(nclk)=1.5 v(vout)=1.199999988079071
+.options method=gear maxord=1 trtol=1e7 reltol=1e-7 vntol=1e-10 abstol=1e-13 gmin=1e-18 itl4=500
+.tran 250p 106.625n 0 250p uic
+.meas tran od find v(od) at=84.5n
+.meas tran te find v(te) at=84.5n
+.meas tran vo_f find v(vout) at=84.5n
+.meas tran vo_h find v(vout) at=88.5n
+.meas tran vo_e find v(vout) at=106.5n
+.print tran v(vout) v(net1) v(net2) v(net3) v(net4) v(net5) v(nclk) v(od) v(te)
+.end