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analog: rename sar_adc Range to ErrRange -- master types ratchet green again (Closes #10891) #10892

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Merged
gHashTag merged 1 commit into from
Oct 19, 2026
Merged

analog: rename sar_adc Range to ErrRange -- master types ratchet green again (Closes #10891) #10892

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12 changes: 6 additions & 6 deletions .trinity/seals/analog_AnalogSarAdc.json
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Original file line number Diff line number Diff line change
Expand Up @@ -11,16 +11,16 @@
}
],
"config": "gen=c,rust,verilog,zig;tests=zig",
"gen_hash_c": "sha256:190cf9c7a9bbc52e2ff243a068d5a52cef270186bb973987eccac07f356766a3",
"gen_hash_rust": "sha256:c022f3879d7688e5ab333d9a2aa777d397f1abc693347dd7d8a53aa44d77d051",
"gen_hash_verilog": "sha256:099481e4176136e97c8f372988dbd2fb9cb69cdfaaf4a3fd6b33a96bc3457a65",
"gen_hash_zig": "sha256:2e98efa78c53a211ce004f0b1480314821d694a39abc8b3091232e4394c1e616",
"gen_hash_c": "sha256:c8621c9cb85a4f0990075a906c901964df0b4c48d37206057ec1d4265ccdea30",
"gen_hash_rust": "sha256:f63529e07003b67b4d34a5a999c0095daae6732a8c3e56093dcb17fcf9573947",
"gen_hash_verilog": "sha256:3281bec146dd8f240de65ffc8a867647645c8a6af1c56303eba2e7fe35289005",
"gen_hash_zig": "sha256:9fa3aa4789bcb6d02177add93c6613f6720c4f7c59b2e6b3e65b3accf66b7048",
"module": "AnalogSarAdc",
"ring": 12,
"seal_schema": 2,
"sealed_at": "2026-10-19T04:48:15Z",
"sealed_at": "2026-10-19T05:44:03Z",
"sealed_by": "t27c-bootstrap@0.5.2",
"spec_hash": "sha256:cedecad9b8f1a481da765debb6c64cc4c9c2a4567953dba05367fe6d7ff76094",
"spec_hash": "sha256:48e8825a4a6a7fc24ce23472bcba5499dcafbd399ac45a14fb153a0a020018e2",
"spec_path": "specs/analog/sar_adc.t27",
"tests": {
"failed": 0,
Expand Down
10 changes: 5 additions & 5 deletions specs/analog/sar_adc.t27
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Original file line number Diff line number Diff line change
Expand Up @@ -357,10 +357,10 @@ pub fn miss_margins(k: []const u32, off: u32, vp: []const f64, vn: []const f64,
return Margins { sum: sum, worst: worst };
}

pub struct Range { lo: f64, hi: f64 }
pub struct ErrRange { lo: f64, hi: f64 }

/// The smallest and the largest signed code error (model - ngspice) over the 31 conversions.
pub fn err_range(k: []const u32, off: u32, vp: []const f64, vn: []const f64) -> Range {
pub fn err_range(k: []const u32, off: u32, vp: []const f64, vn: []const f64) -> ErrRange {
var lo : f64 = 0.0;
var hi : f64 = 0.0;
var i : usize = 0;
Expand All @@ -371,7 +371,7 @@ pub fn err_range(k: []const u32, off: u32, vp: []const f64, vn: []const f64) ->
if (e > hi) { hi = e; }
i = i + 1;
}
return Range { lo: lo, hi: hi };
return ErrRange { lo: lo, hi: hi };
}

; --- the fit: two numbers the merged blocks do not have ---------------------------------------------------------------------
Expand Down Expand Up @@ -534,7 +534,7 @@ test the_merged_blocks_as_they_are_match_none_of_the_conversions_and_the_error_h
i = i + 1;
}
// model - ngspice: the model is 12 codes above ngspice at the low end of the sine and 21 codes below it at the high end
const r : Range = err_range(&k0, 0, &S_VP, &S_VN);
const r : ErrRange = err_range(&k0, 0, &S_VP, &S_VN);
assert_eq(r.lo, 0.0 - 21.0);
assert_eq(r.hi, 12.0);
// the error is a straight line, a gain and an offset: ngspice's code about the middle (1023.5) is a times the model's plus b, by
Expand Down Expand Up @@ -613,7 +613,7 @@ test with_the_top_plate_parasitic_and_the_comparator_offset_30_of_31_conversions
const mm : Margins = miss_margins(&kf, off, &S_VP, &S_VN, 2);
assert(mm.worst < 0.0003);
assert(mm.worst > 0.0001);
const r : Range = err_range(&kf, off, &S_VP, &S_VN);
const r : ErrRange = err_range(&kf, off, &S_VP, &S_VN);
assert_eq(r.lo, 0.0 - 1.0);
assert_eq(r.hi, 0.0);
// one LSB of the 11-bit code is VDD / 1023 = 1.466 mV: the misses are within 0.15 of it
Expand Down
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