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elab baseline: add systolic 0 so master fpga-conformance is green again (Closes #11099) - #11100
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#11094 made specs systolic generate Verilog that iverilog elaborates with 0 errors. The ratchet reads a generated module absent from the baseline as NEW and fails, even at 0: master's fpga-conformance has been red on fcb3bc5 with "elaboration errors: 214 (baseline 214)" and "NEW systolic: 0 errors, not in baseline". Produced by tools/check_elab_ratchet.py --update-baseline on a t27c with master's compiler.rs digest (e34e1b174c96, == FROZEN_HASH); the verify run matched CI's numbers exactly. The calibration comment stays iverilog 12.0 (CI's version): every other count is identical under 13.0. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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October 19, 2026 16:57
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Closes #11099
Master's
fpga-conformancehas been red since #11094: systolic now elaborates with 0 errors, but the gate reads a generated module that is absent fromtools/elab_baseline.txtas NEW (elaboration errors: 214 (baseline 214),NEW systolic: 0 errors, not in baseline).One added line:
systolic 0. It comes fromtools/check_elab_ratchet.py --update-baselineon a t27c with master's compiler.rs digest; the verify run before the update matched CI's numbers exactly. The calibration comment staysiverilog-version 12.0(CI's version); every other count is identical under the local 13.0.Not fixed here:
spec-guardsandcoveragestay red on master until the Linux seal re-save in #11097.Checks: the four required ones decide this PR; the data change has no code in it.
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