gHashTag · Oct 19, 2026 · Oct 19, 2026
@@ -0,0 +1,53 @@
+{
+  "built_by": "t27c-bootstrap@0.5.2+42a4860c4",
+  "closure": [
+    {
+      "spec": "specs/analog/linear.t27",
+      "spec_hash": "sha256:3ddef7be183aba583ed285334ee389b48a65b41335e98914514235db7c4e5d62"
+    },
+    {
+      "spec": "specs/analog/mos_psp103_50c_data.t27",
+      "spec_hash": "sha256:9e68629797a29516836ca3e0b5e4881b0e751d847c58fd52b63e8f69746dbbe1"
+    },
+    {
+      "spec": "specs/analog/mos_psp103_data.t27",
+      "spec_hash": "sha256:3936594d2ab220f06b2d636182689811b696e044fc3ce6850ea2604ac74f3ea3"
+    },
+    {
+      "spec": "specs/analog/mos_table.t27",
+      "spec_hash": "sha256:16d28f10fa8663926dddb4bcced981cdc4cd8f38a6b748e4b7688f2e56bbab6c"
+    },
+    {
+      "spec": "specs/analog/sar_cdac.t27",
+      "spec_hash": "sha256:a7c45039214a8b2e92333a88befc95af33ff482ce08af3be97e2c5b8be3eacd3"
+    },
+    {
+      "spec": "specs/analog/sar_kick.t27",
+      "spec_hash": "sha256:8c7c3968475c3f62c78f7b0a7739c2f049680eb9911d23be7f4d0ce0a4922dff"
+    }
+  ],
+  "config": "gen=c,rust,verilog,zig;tests=zig",
+  "gen_hash_c": "sha256:8cb91e670ed91a22726cec0defd9e5edd7abc3899c0180bfe974425b7694adda",
+  "gen_hash_rust": "sha256:ddc364af3bf9d50c1aa3ddc1a56d4172316f9bac6a009b065c80fc84e1ee62e4",
+  "gen_hash_verilog": "sha256:9a0c3536cde4c2cbfea630b9e999c6396c4e93efaec1abc64af39ab41153609c",
+  "gen_hash_zig": "sha256:ab44ba61d3d916294e8a4b3c754d411d9e168192dfecb06ce6ad9dff36955cb6",
+  "module": "AnalogSarKickNet",
+  "ring": 12,
+  "seal_schema": 2,
+  "sealed_at": "2026-10-19T18:11:39Z",
+  "sealed_by": "t27c-bootstrap@0.5.2",
+  "spec_hash": "sha256:54ed560c6e5fda7f9e497d03546dd36300d0b0e14da99dc3284bb76136bbf3b6",
+  "spec_path": "specs/analog/sar_kick_net.t27",
+  "tests": {
+    "failed": 0,
+    "failing": [],
+    "forced": false,
+    "passed": 20,
+    "total": 20,
+    "vacuous": 0
+  },
+  "toolchain": {
+    "test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
+    "zig": "0.16.0"
+  }
+}
@@ -5,8 +5,10 @@ The golden comparator's aperture: how much a step of its input at time tau still
 * small step and the ratio of the response to a step at tau to the response to a step before the edge is the share of the decision that the input still decides at tau: 1 until the pair
 * begins to lose its gain and 0 once the latch has locked. The kick of the comparator's own plates moves VDP - VDN through that window, and sar_kick_net.t27 weighs it by this aperture.
 * The unperturbed run has dp = dn (the plates are alike); the steps at 98.3069 ns (before the edge), at 0.5 mV and at 2 mV, give the same response to 0.1 percent (LINEAR rows).
-* Paths are NOT in this file: IHP_PDK, IHP_OSDI and SAR_GOLDEN_SUBCKTS as in sar_kick_edge.cir. Run: ngspice -b sar_kick_aperture.cir   (ngspice-47, about two minutes)
-* It prints one row per tau between BEGIN aperture and END aperture: tau - 99.3069 ns (the clkc 0.1 V crossing of the unperturbed run) in ns, and the response in volts.
+* Paths are NOT in this file: IHP_PDK, IHP_OSDI and SAR_GOLDEN_SUBCKTS as in sar_kick_edge.cir. Run: ngspice -b sar_kick_aperture.cir   (ngspice-47, 20 transients of 107 ns at 50 ps)
+* It prints, between BEGIN aperture and END aperture, the rows APERTURE tau (tau is absolute: the step at 98.3069 ns, 1 ns before the clkc 0.1 V crossing of the unperturbed run at
+* 99.3069 ns, then at 102.3069 ns + 0.125 ns j, 3.0 ns + 0.125 ns j after it, j = 0 .. 15, dv = 1 mV) and LINEAR dv (the step at 98.3069 ns at dv = 0, 0.5 mV, 2 mV), each with dd = v(x3.dp)
+* and de = v(x3.dn) at 104.1069 ns in volts. The share of the decision at tau is ((dd - de) - the dv = 0 difference) over the same of the row at 98.3069 ns.
 .param vg=0.742
 .param tp=14n
 .param tau=1

@@ -0,0 +1,77 @@
+A moved bit's drive: the two-port the bottom-plate drivers present at Bit and Bit_n after the bit's decision, both directions (M4e-kick, #10942)
+* specs/analog/decks/sar_kick_cnode_moved.cir -- sar_kick_cnode.cir with the bit MOVED instead of idle: the clock CK11 of DAC_control and neg_bottom_plate_logic high (the tgate x2 to VCM
+* and x11 between the plates are off; the inverter XM3 / XM4 holds Bit, and the inverter x12 behind the tgate x15 holds Bit_n), the bit's flip-flop forced by Set or Reset, and each plate node
+* held 10 mV off its rail, where the plates sit (they kick by tens of millivolts about it). Two cases: dir 0, the P plate UP (Bit at 1.49 V through the pmos, Bit_n at 0.01 V through the
+* inverter x12's nmos and the tgate x15's nmos), dir 1, the P plate DOWN (Bit at 0.01 V through the nmos, Bit_n at 1.49 V through two pmos). The operating point gives the on-resistances as 10 mV / i:
+* the P plate 1881 ohm up (pmos W 3 um) and 1428 ohm down (nmos W 1 um), the N plate 2862 and 3772 ohm, twice the inverter's: the golden tgate x15 at a rail is one device of the inverter's size
+* again. The ac runs at 100 MHz and 300 MHz give, as sar_kick_cnode.cir does, the admittance matrix Y = G + j w C of the two plate nodes of the moved bit, the capacitances its devices add.
+* Paths are NOT in this file: IHP_PDK, IHP_OSDI and SAR_GOLDEN_SUBCKTS as in sar_off_base.cir. Run: ngspice -b sar_kick_cnode_moved.cir   (ngspice-47, seconds). TEMP 50 as in the golden deck.
+* It prints, between BEGIN y and END y, per direction: DIR d, the operating point's currents i(vpb), i(vnb) (A) and then, per frequency, PORT1 / PORT2 with the two printed currents of the
+* sources VPB and VNB (A, volts are 1, as in sar_kick_cnode.cir).
+.lib $IHP_PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+.lib $IHP_PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib cap_typ
+.include $SAR_GOLDEN_SUBCKTS
+VDD vdd 0 1.5
+VCM vcm 0 0.75
+VCK ck 0 1.5
+VIN vin 0 0.75
+VCLK clks 0 0
+VST set 0 {vset}
+VRS reset 0 {vrst}
+XD vdd 0 sar vcm bitp vin ck set reset clks DAC_control
+XN vdd 0 ck bitp bitn neg_bottom_plate_logic
+VPB bitp 0 {vpb} ac 1
+VNB bitn 0 {vnb} ac 0
+.param vset=0
+.param vrst=0
+.param vpb=1.49
+.param vnb=0.01
+.options temp=50
+.control
+pre_osdi $IHP_OSDI/psp103.osdi
+pre_osdi $IHP_OSDI/psp103_nqs.osdi
+set numdgt=8
+echo BEGIN y
+alterparam vset = 0
+alterparam vrst = 1.5
+alterparam vpb = 1.49
+alterparam vnb = 0.01
+reset
+op
+echo DIR 0
+print i(vpb) i(vnb)
+foreach fr 1e8 3e8
+  alter vpb ac = 1
+  alter vnb ac = 0
+  ac lin 1 $fr $fr
+  echo PORT1 $fr
+  print i(vpb) i(vnb)
+  alter vpb ac = 0
+  alter vnb ac = 1
+  ac lin 1 $fr $fr
+  echo PORT2 $fr
+  print i(vpb) i(vnb)
+end
+alterparam vset = 1.5
+alterparam vrst = 0
+alterparam vpb = 0.01
+alterparam vnb = 1.49
+reset
+op
+echo DIR 1
+print i(vpb) i(vnb)
+foreach fr 1e8 3e8
+  alter vpb ac = 1
+  alter vnb ac = 0
+  ac lin 1 $fr $fr
+  echo PORT1 $fr
+  print i(vpb) i(vnb)
+  alter vpb ac = 0
+  alter vnb ac = 1
+  ac lin 1 $fr $fr
+  echo PORT2 $fr
+  print i(vpb) i(vnb)
+end
+echo END y
+.endc
+.end
@@ -0,0 +1,139 @@
+The golden SAR ADC's sine run, the comparator's clock edge at six decisions: the tail node and the drain of the input pair before and through the edge (M4e-kick, #10942)
+* specs/analog/decks/sar_kick_late.cir -- sar_off_base.cir (the golden SAR ADC deck of uberWAVE, wp2-parser/golden/top.spice, GPL-2.0: fetched at run time, never vendored; its subcircuits
+* come from the run-time file SAR_GOLDEN_SUBCKTS, made as in sar_off_base.cir) with nothing changed in the circuit and a different readout: the golden sine (sar_amp 0.6, the first two conversions,
+* 1.1 us) and, at the clock edge of six of its 22 decisions, the waves that sar_kick_edge.cir reads at the first decision with the two gates on ideal sources: the tail node net1 and the drain ap of
+* the comparator's input pair, and the plates vdp and vdn, 67 samples 0.1 ns apart. The edge is clkc rising through 0.1 V (tcb) and through 0.75 V (tcc); sample k is at (j0 + 2 k) * 50 ps
+* of the 50 ps grid that `linearize` makes, j0 = floor(tcb / 50 ps) - 30, that is 1.5 ns to 1.55 ns before the 0.1 V crossing, to 5.05 ns after it. The six are the clkc rises 1, 10, 11
+* (decisions 0, 9 and 10 of the first conversion) and 12, 21, 22 (the same of the second); the first of each conversion has the sine's plates settled for 14 ns, the last two have nine and ten
+* bottom plates moved. Like sar_kick_edge.cir this is the comparator's own history (what net1 and ap do before and through the edge), read where it happens, and sar_kick_net.t27 puts it
+* through the same charge tables.
+* Paths are NOT in this file: IHP_PDK (the IHP-Open-PDK checkout, commit 21133f21), IHP_OSDI (the directory with the compiled psp103.osdi, psp103_nqs.osdi, r3_cmc.osdi, mosvar.osdi,
+* cap_cmomi.osdi, cap_cmomf.osdi) and SAR_GOLDEN_SUBCKTS, in the environment. Run: IHP_PDK=<checkout> IHP_OSDI=<osdi dir> SAR_GOLDEN_SUBCKTS=<file> ngspice -b sar_kick_late.cir   (ngspice-47, the
+* transient of 1.1 us at 50 ps is the long part of it: minutes on a few cores). It prints, between BEGIN late and END late, per window: the decision's clkc rise number rr, the crossing times
+* tcb and tcc in seconds, j0, the plates' difference vdp - vdn at the 0.1 V crossing (vpt - vnt, to compare with D of sar_kick.t27's DEC_D), and the four waves n1w, apw, vpw, vnw.
+.param dmv=0
+.param amp=0.6
+.lib $IHP_PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+.lib $IHP_PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerCAP.lib cap_typ
+.include $SAR_GOLDEN_SUBCKTS
+* supplies, trim code A B C = 0 0 0, the common mode, the sampling clock and the differential sine input
+VDD4 vdda 0 1.5
+VDD6 vdd 0 1.5
+VDD7 vcm 0 0.75
+V2 c 0 0
+V5 b 0 0
+V6 a 0 0
+VDD1 vss 0 0
+VCMS net2 0 0.75
+VCLKS clks 0 PULSE(0 1.5 0n 2n 2n 80n 500n)
+VSP net2 vinp sin({-dmv*0.5e-3} {amp} 62.5k)
+VSN vinn net2 sin({-dmv*0.5e-3} {amp} 62.5k)
+* the two tracking switches, the comparator, the SAR logic and the clock generator
+x1 vdda 0 vinn vdn clks tracking_switch
+x2 vdda 0 vinp vdp clks tracking_switch
+x3 vocp vocn valid vdp vdn clkc vdd 0 dynamic_comparator_top
+x7 ck3 ck11 ck7 ck2 ck6 ck10 ck1 ck9 ck5 ck8 ck4 vdd 0 vdd valid 0 clks SAR_logic
+x4 vdd clkc 0 clks valid ck1 a b c clock_gen
+* the 4 fF loads the golden top hangs on the top plates and on the control nets
+C3 vdp 0 4f
+C4 vdn 0 4f
+C5 vdp 0 4f
+C6 vdn 0 4f
+C7 vinp 0 4f
+C8 vinn 0 4f
+C9 clkc 0 4f
+C10 vocp 0 4f
+C11 valid 0 4f
+C12 vocn 0 4f
+C13 clkc 0 4f
+C14 clks 0 4f
+C15 valid 0 4f
+C16 ck1 0 4f
+C17 a 0 4f
+C18 b 0 4f
+C19 c 0 4f
+C20 clks 0 4f
+C21 valid 0 4f
+C22 vdd 0 4f
+* the bottom-plate drivers (every stage decides on vocn), then the negated copy of each bit for the N half
+x5 vdd bit_10 vocn 0 ck11 vcm out_11 0 0 clks bit_9 vocn ck10 out_10 bit_8 vocn ck9 out_9 bit_7 vocn ck8 out_8 bit_6 vocn
++ ck7 out_7 bit_5 vocn ck6 out_6 bit_4 vocn ck5 out_5 bit_3 vocn ck4 out_4 bit_2 vocn ck3 out_3 bit_1 vocn ck2 out_2 bit_0 vocn ck1
++ out_1 DAC_control_top
+x6 vdd vss ck11 bit_10 bit_10_n neg_bottom_plate_logic
+x8 vdd vss ck6 bit_5 bit_5_n neg_bottom_plate_logic
+x9 vdd vss ck10 bit_9 bit_9_n neg_bottom_plate_logic
+x10 vdd vss ck5 bit_4 bit_4_n neg_bottom_plate_logic
+x11 vdd vss ck9 bit_8 bit_8_n neg_bottom_plate_logic
+x12 vdd vss ck4 bit_3 bit_3_n neg_bottom_plate_logic
+x13 vdd vss ck8 bit_7 bit_7_n neg_bottom_plate_logic
+x14 vdd vss ck3 bit_2 bit_2_n neg_bottom_plate_logic
+x15 vdd vss ck7 bit_6 bit_6_n neg_bottom_plate_logic
+x16 vdd vss ck2 bit_1 bit_1_n neg_bottom_plate_logic
+* the deck's own output adder: V(out) = 1.5 V code / 2048 with the bits at 0 / 1.5 V
+E1 out net12 out_11 0 0.5
+E2 net12 net11 out_10 0 0.25
+E3 net11 net10 out_9 0 0.125
+E4 net10 net9 out_8 0 0.0625
+E5 net9 net8 out_7 0 0.03125
+E6 net8 net7 out_6 0 0.015625
+E7 net7 net6 out_5 0 0.0078125
+E8 net6 net5 out_4 0 0.00390625
+E9 net5 net4 out_3 0 0.001953125
+E10 net4 net3 out_2 0 0.0009765625
+E11 net3 0 out_1 0 0.00048828125
+* the two capacitive DAC halves: the N half on VDN with the negated bits, the P half on VDP
+x17 vdn bit_3_n bit_8_n bit_5_n bit_6_n bit_7_n bit_4_n bit_9_n bit_10_n bit_2_n bit_1_n Diff_cap_DAC
+x18 vdp bit_3 bit_8 bit_5 bit_6 bit_7 bit_4 bit_9 bit_10 bit_2 bit_1 Diff_cap_DAC
+.ic v(x1.net1)=0
+.ic v(x1.net2)=0
+.nodeset v(x1.net2)=0
+.ic v(x1.net3)=0
+.ic v(x2.net1)=0
+.ic v(x2.net2)=0
+.ic v(x2.net3)=0
+.ic v(x17.net1)=0
+.ic v(x18.net1)=0
+.ic v(vdp)=0
+.ic v(vdn)=0
+.options temp=50
+.options klu
+.save v(vdp) v(vdn) v(clkc) v(x3.x1.ap) v(x3.x1.net1)
+.control
+pre_osdi $IHP_OSDI/psp103.osdi
+pre_osdi $IHP_OSDI/psp103_nqs.osdi
+pre_osdi $IHP_OSDI/r3_cmc.osdi
+pre_osdi $IHP_OSDI/mosvar.osdi
+pre_osdi $IHP_OSDI/cap_cmomi.osdi
+pre_osdi $IHP_OSDI/cap_cmomf.osdi
+set num_threads=2
+tran 0.05n 1.1u
+linearize v(clkc) v(x3.x1.net1) v(x3.x1.ap) v(vdp) v(vdn)
+set numdgt=8
+set noprintscale
+echo BEGIN late
+foreach rr 1 10 11 12 21 22
+  meas tran tcb when v(clkc)=0.1 rise=$rr
+  meas tran tcc when v(clkc)=0.75 rise=$rr
+  meas tran vpt find v(vdp) when v(clkc)=0.1 rise=$rr
+  meas tran vnt find v(vdn) when v(clkc)=0.1 rise=$rr
+  let j0 = floor(tcb / 5e-11) - 30
+  let n1w = unitvec(67)
+  let apw = unitvec(67)
+  let vpw = unitvec(67)
+  let vnw = unitvec(67)
+  let k = 0
+  while k < 67
+    let j = j0 + 2*k
+    let n1w[k] = v(x3.x1.net1)[j]
+    let apw[k] = v(x3.x1.ap)[j]
+    let vpw[k] = v(vdp)[j]
+    let vnw[k] = v(vdn)[j]
+    let k = k + 1
+  end
+  echo WINDOW $rr
+  print tcb tcc j0 vpt vnt
+  print n1w apw vpw vnw
+end
+echo END late
+.endc
+.end