docs(analog): night report addendum 2 (weak inversion, PR 11146) and two lessons into analog-emulation (Updates #11062)

.claude/skills/analog-emulation/SKILL.md

@@ -131,3 +131,5 @@ The page is a single HTML file whose data sits in four arrays at the top of its
 - 2026-10-19 VACASK: the PyPI wheel vacask-bin (0.3.4.dev3) reads main-branch syntax in a container with python3 and no install rights; the 0.3.4 release tarball needs libopenblas; the IHP PDK converter comes from a main-branch clone (12 s, no hand edits); the hb analysis of a demo newer than the wheel stops with an unknown parameter. (#10911)
 - 2026-10-19 VACASK decks: a top-level var is a syntax error (use it in the control block); integer sweep values divide as integers (write the divisor as a real); uic mode starts an unlisted node at 0 V even if a source drives it; a module_path_prefix in the toml replaces the PDK osdi directory, so list both; one failing sweep point aborts the whole sweep. (#10911)
 - 2026-10-19 Comparing two simulators: take crossings from the clock edge on, not from ngspice meas (it misses the first-step jump to about 1.2 V that both show, and prints 6 digits); ngspice print times are the adaptive grid, so take the last point inside the interval. (#10911)
+- 2026-10-19 t27b can pass while t27c test-report (Zig) panics, here on a 39-bit shift of a u64 value: run test-report as well as t27b before landing; t27b does not take f64 as u64, and a failing assert_eq on an f64 prints its raw bit pattern. (#10881)
+- 2026-10-19 The test runner folds an assert on constant array words into no runtime assert (the test reads VACUOUS): read test data through variables; ngspice cross-plot references (dc1.l0n[k]) work only while the plots are named dc1, dc2, so the deck must say so. (#10881)

docs/analog/night-report-2026-10-19.md

@@ -48,7 +48,7 @@ Every PR above is merged. A lane for #10911 (VACASK as a second reference) was s
 
 ## 4. Weak points and competitors
 
-- Analog (PR #11071, section 11 of `docs/analog/competitors.md`): W1 reduced (exact zero-order hold for the linear cell, amplitude ratio 1.0003 against 1.78e-7 for backward Euler; the nonlinear path is still backward Euler); W2 open (no stiffness report, steps chosen by hand); W3 reduced (charge tables for tt and ss in PR #10893, then ff, fs and sf in PR #11123: all five corners, inverter delays within 0.025 %); W4 reduced (five corners within 0.56 % where Id is at least 100 uA, weak inversion not met); W5 reduced; W6 reduced; W7 open (no speed claim is allowed); W8 reduced; W9 reduced (RAW writer byte-equal to ngspice's); W10 reduced. Nine more weak points found while building are listed as W11 onward.
+- Analog (PR #11071, section 11 of `docs/analog/competitors.md`): W1 reduced (exact zero-order hold for the linear cell, amplitude ratio 1.0003 against 1.78e-7 for backward Euler; the nonlinear path is still backward Euler); W2 open (no stiffness report, steps chosen by hand); W3 reduced (charge tables for tt and ss in PR #10893, then ff, fs and sf in PR #11123: all five corners, inverter delays within 0.025 %); W4 reduced (five corners within 0.56 % where Id is at least 100 uA; weak inversion met for tt in PR #11146, see section 12); W5 reduced; W6 reduced; W7 open (no speed claim is allowed); W8 reduced; W9 reduced (RAW writer byte-equal to ngspice's); W10 reduced. Nine more weak points found while building are listed as W11 onward.
 - Lab (PR #11072, `docs/lab/competitors.md`): volunteer computing, compute markets, remote build execution and mobile limits; the design's weak points are the cost of k-of-n verification, Sybil and collusion, floating-point determinism, untrusted code, node supply at cold start, mobile limits and the legal line.
 
 ## 5. Decomposition
@@ -118,3 +118,9 @@ At all 14 inputs the decision time agrees within 0.125 ps, the resolution time w
 Effect on option A: its first step, a second independent reference on the golden comparator, is done; what the external team's input still adds is a VACASK newer than the wheel (so their demo runs in full) and their evaluator's limits.
 
 A defect a peer found (PR #11136, issue #11131). Another session reported that my lab L2 spec `lab_t27b_ratchet.t27` made the `t27b-native-ratchet` of every PR read "jit/interp mismatch 1". `t27b test --check` reproduces it: the JIT passes, the interpreter faults on an 8-byte read of bytes never written. Nine `[3]usize` scratch arrays were declared without a value; they now start at zero; `--check` exits 0 and the interpreter runs 1824 runtime asserts instead of stopping at 794. I had not run `--check` on that spec; the landing script now does for every spec.
+
+## 12. Addendum (02:45): weak inversion, PR #11146 (issue #10881, merged)
+
+The log-domain reader (ln Id in 1/65536 octave at each node of a 97 x 49 grid, a 129-entry exp table and a shift, the weak-inversion Vds factor read apart, the slope read off the same words) meets the 1 percent bar in weak inversion for the tt corner. Relative error with the 1e-9 A floor, NMOS W 1.0 um and PMOS W 3.0 um: 0.080 % and 0.094 % at the 576 cell midpoints, 0.398 % and 0.527 % at the 1000 held-out points, 0.467 % and 0.705 % at the 1000 cell centres (the worst place for a chord of the new grid); the M3b linear reader on the same points stays at 0.5 to 0.73. The integer read is within 0.102 % of its f64 twin.
+
+The tt inverter against ngspice backward Euler, log current tables with the M3c drain charge: 500 fF at dt 100 ps rising 0.0018 %, falling 0.025 %; 10 pF at dt 2 ns 0.0014 % and 0.0033 % (with the 500 fF charge tables scaled by 1/20; without charge that run is 0.163 % and 0.189 % off, which the reader does not change). The DC transfer is 0.17 mV off against 5.5 mV before. Ten specs tested, 0 FAIL, 0 vacuous; `t27b test --check` shows 0 mismatches on all ten. Not done: log tables for the corners other than tt, and a gm for the log tables. Effect on section 4: of W4 (weak inversion not met) the tt part is now met.