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analog M5e: the SAR inverter delays into 20 fF from the PSP103 tables with charge, within 0.52 percent of ngspice; acceptance 8 PASS, 0 FAIL, 5 NOT MODELLED - #11374
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…-- fall 75.755 ps and rise 93.246 ps, +0.51 and +0.50 percent from ngspice's converged run (75.368 and 92.778 ps), accept_sar now 8 PASS, 0 FAIL, 5 NOT MODELLED of 13 blocks (Closes #11350) specs/analog/mos_psp103_inv20.t27 (new): the inverter of the golden SAR netlist (PMOS 3.0 um, NMOS 1.0 um, L 0.45 um, m 1, bulks on the rails: the sizes of the header of mos_psp103.t27 and of psp103_inv_be_500f.cir) into 20 fF on the tt 27 C PSP103 log tables with the M3c drain charge, the backward Euler equation of newton_iter_q, and an output node free to leave 0 .. Vdd: an ideal gate edge kicks it 0.40 V below ground and 0.50 V over the supply, where the two ends of the channel exchange their roles and the source terminal's charge is on the output. The current is sq_i, the charge sq_qt and sq_qsrc of sar_comparator_q.t27 (reused, not copied); each source is on its own bulk so the Vsb axis is read at 0, the 2-D read bit for bit (a test). One step is solved by bisection. Delays, ideal gate step, 1 ps step: fall 75.755 ps, rise 93.246 ps against ngspice-47 converged 75.368 and 92.778 ps (+0.513 and +0.504 percent; the bar is 10). Halving the step: 4, 2, 1, 0.5, 0.25 ps give 93.485, 93.324, 93.246, 93.210, 93.191 (rise) and 75.971, 75.826, 75.755, 75.720, 75.703 (fall); 1 ps against 0.5 ps moves them by 0.039 and 0.046 percent (the issue asks under 1). Waveform within 11.3 mV (rise) and 35.0 mV (fall) of ngspice's 20 samples per edge, both at the first sample, and within 6 mV from 30 ps on. The same code at 500 fF and 100 ps reproduces ngspice's backward Euler to -0.0022 and -0.026 percent. Negative controls: charge removed 39.0 and 51.9 ps (-48 and -44 percent, inside the report's 1 to 500 ps and refused by the bar); output held to 0 .. Vdd 46.8 and 63.1 ps (-38 and -32 percent); a load of 25 fF +13.5 and +14.5 percent. specs/analog/decks/psp103_inv20_fine.cir (new): the cell into 20 fF in ngspice-47 with the PSP103, an ideal gate step, trapezoidal rule with the step held to 0.05 ps (and 0.2 and 0.01 ps: the same crossings to 1 fs), the crossings, the rest levels, the kick and 20 samples after each edge. accept_sar.t27: the inverter's delay row measured, a row PASS only inside the report's limit AND within 10 percent of ngspice, the block a PASS, counts 8 / 0 / 5 blocks and 24 / 0 / 6 rows; the corners test sees the charge-removed control too. docs/analog/accept-sar-2026-10-20.md: counts, table, section 3e, controls. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
… with charge, within 0.52 percent of ngspice; acceptance 8 PASS, 0 FAIL, 5 NOT MODELLED (Closes #11350) Merge of master plus sealing, gates run on the merged tree with t27c from master: tests clean with vacuous passes 0, seal --verify MATCH, tri types ratchet CLEAN, dupe_scan failure set a subset of master's. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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October 20, 2026 12:39
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Closes #11350
analog M5e: the SAR inverter delays into 20 fF from the PSP103 tables with charge, within 0.52 percent of ngspice; acceptance 8 PASS, 0 FAIL, 5 NOT MODELLED
Gates run on the merged tree (t27c from master): 2 spec(s) with tests clean and vacuous passes 0, seal --verify MATCH, tri types ratchet CLEAN, dupe_scan failure set a subset of master's (inherited red).
TEST specs/analog/mos_psp103_inv20.t27 tests=[10] fail=[0] vacuous=[0]
TEST specs/analog/accept_sar.t27 tests=[15] fail=[0] vacuous=[0]
SEAL specs/analog/mos_psp103_inv20.t27 :: all hashes MATCH
SEAL specs/analog/accept_sar.t27 :: all hashes MATCH
TYPES RATCHET: CLEAN
DUPE failing=4 extra-vs-master=[]
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