t27b verilog README: libraries, --top, signed, tables, constant divis…

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GitGuardian

GitGuardian Security Checks

PR budget (at most 20 open ready PRs per author; the excess waits as a draft) on: pull_request_target 3

budget

Duplicate Body Ratchet on: pull_request 6

duplicate-bodies

Withdrawn Number Gate on: pull_request 2

withdrawn-live

Documented Commands on: pull_request 2

Documented t27c subcommands exist

t27b native on: pull_request 6

t27b-native-linux

t27b-native-macos

t27b-native-ratchet

Verilog Widths on: pull_request 3

Verilog widths (absurd-width ledger)

Issue Gate on: pull_request_target 2

check-linked-issue

Spec Guards on: pull_request 11

spec-guards

Seal Coverage on: pull_request 2

coverage

Untrusted Input Gate on: pull_request 1

untrusted-input

PR Dashboard on: pull_request 1

pr-dashboard

Gate Topology on: pull_request 4

gate-topology

claw-t27f

claw-sarif

claw-suggest

claw-merge

claw-batch

Conflict Markers on: pull_request 2

Conflict markers (no unresolved merges)

FPGA E2E Build on: pull_request 14

fpga-smoke

fpga-lint (read_verilog + hierarchy)

fpga-synthesis

fpga-synthesis-arty

fpga-formal

fpga-conformance

fpga-bitstream

fpga-report

PHI Loop CI on: pull_request 1

phi-loop-check

cli-tri on: pull_request 3

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L1 TRACEABILITY Check on: pull_request 4

Check L1 TRACEABILITY

L1 Traceability Summary

Corpus Ratchet on: pull_request 2

Corpus ratchet (expected-failure ledger)

secret-scan on: pull_request 2

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loop-tools-gate on: pull_request 4

loop-tools-tracked

harness

Damage Negatives on: pull_request 2

Damage negatives (false-positive fixtures)

Harness scratch directories on: pull_request 2

No test binary shares one scratch directory

Fix Carries Source on: pull_request 1

fix-carries-source

Spec Parse Ratchet on: pull_request 2

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Schema Validation on: pull_request 2

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Own Language on: pull_request 1

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Emit Bit-Exact Gate (CI-02) on: pull_request 2

emit-bitexact

Orphaned modules on: pull_request 2

Every source file is reachable from its crate root

PR budget (at most 20 open ready PRs per author; the excess waits as a draft) on: pull_request_target 3

budget

t27b verilog README: libraries, --top, signed, tables, constant divis…

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