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analog M3f phase 2a: the comparator device evaluation as a clocked unit, bit for bit the spec at 810 evaluations; one unit with its NMOS table ROM routed on xc7a200tfbg484-2: 14208 LUT, 5228 FF, 15 DSP48E1, 105 RAMB18 + 2 RAMB36, 59.46 MHz post-route; 506 to 674 clocks per full evaluation - #11427
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…aluations and one node update in exact integer words -- 613.074 and 613.151 ps, the model's own, 23 to 31 table reads and 141 to 185 multiplications an evaluation (Refs #11380) specs/analog/sar_comparator_qi.t27 (new; nothing existing is edited). The step of sar_comparator_q.t27 is already exact integer arithmetic (u32 words, sign-magnitude u64, 64-bit elimination); the f64 in that file is its judge, so the integer step is that step and the decision times are 613.0742 ps (+2 mV) and 613.1508 ps (-2 mV), 0.0007 and 0.0001 percent from the issue's 613.07 and 613.15, every sample, fold, residual and time those of sq_run, the 2125 step reset run too. FR-001: qi_eval / qi_scatter / qi_assemble / qi_update / qi_iter / qi_step / qi_run, reusing sq_i, sq_fd, sq_qt, sq_slope, sq_qsrc, sq_mul, the stamps and the 8 x 8 solve by `use`. Within 0.5 percent of 613.07 / 613.15 with the sign right at both inputs; negative control: the charge removed decides at 5.40 ps and is refused. FR-002: one Newton iteration is 15 evaluations that read only their own terminals and write one 15-word record each, then one assembly and one node update. Tests: a record is unchanged when a non-terminal node moves and changes when a terminal moves; an evaluation writes nothing but its own slot; five pairs of evaluation/assembly orders give the same 144 registers, the same previous charges and the same nodes after an iteration, bit for bit; whole runs reversed and shuffled fold to the natural fold; leaving out any one of the 15 devices changes the registers. Cost, counted off 876 steps: a full device evaluation is 23 to 31 table reads and 141 to 185 multiplications, a charge-only one 6 to 14 and 39 to 79, a step (75 evaluations) 1518 to 1690 reads and 9517 to 10265 multiplications plus 4 node updates of 224 multiplications and 36 divisions (the loop nest's bound). No speed claim. t27c test-report: 8 tests, FAIL 0, vacuous 0; t27b test --check --quiet exit 0. Phase 2 (the board top) is open. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
…bit with the model, 15 independent device evaluations per iteration (Closes #11386) Merge of master plus sealing, gates run on the merged tree with t27c from master: tests clean with vacuous passes 0, seal --verify MATCH, tri types ratchet CLEAN, dupe_scan failure set a subset of master's. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
… AX7203, one device's qi_eval as a machine with a two-product multiply-add, tables in a ROM beside it (Closes #11380) The unit lowers to Verilog with t27b (rung 1); its phases are written but not yet run against the spec, one test checks the slot program against qi_qt_ext. The board top, the tables' ROM modules, the solver and the receipt are not written. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
…ll 15 devices at 18 steps of the +2 mV run and 6 of the -2 mV run, 15 record words and the 72 matrix entries of their 20 stamps equal to qi_eval and qi_scatter, a flipped table word is seen (Closes #11380) Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
…nd routed -- 9850 LUT, 5084 FF, 15 DSP48E1 for the logic, 54.5 RAMB36 for the ROM of one device kind, 59.46 MHz post-route against 100 asked, 506 to 674 clocks a full device evaluation (Closes #11380) Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
… of its own copy of the body -- the duplicate-bodies gate, same words, same Verilog logic (Closes #11380) Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
…it, bit for bit the spec at 810 evaluations; one unit with its NMOS table ROM routed on xc7a200tfbg484-2: 14208 LUT, 5228 FF, 15 DSP48E1, 105 RAMB18 + 2 RAMB36, 59.46 MHz post-route; 506 to 674 clocks per full evaluation (Closes #11425) Merge of master plus sealing, gates run on the merged tree with t27c from master: tests clean with vacuous passes 0, seal --verify MATCH, tri types ratchet CLEAN, dupe_scan failure set a subset of master's. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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Closes #11425
analog M3f phase 2a: the comparator device evaluation as a clocked unit, bit for bit the spec at 810 evaluations; one unit with its NMOS table ROM routed on xc7a200tfbg484-2: 14208 LUT, 5228 FF, 15 DSP48E1, 105 RAMB18 + 2 RAMB36, 59.46 MHz post-route; 506 to 674 clocks per full evaluation
Gates run on the merged tree (t27c from master): 4 spec(s) with tests clean and vacuous passes 0, seal --verify MATCH, tri types ratchet CLEAN, dupe_scan failure set a subset of master's (inherited red).
TEST specs/fpga/sar_cmp_qi_unit.t27 tests=[6] fail=[0] vacuous=[0]
TEST specs/fpga/sar_cmp_qi_tab_n.t27 tests=[1] fail=[0] vacuous=[0]
TEST specs/fpga/sar_cmp_qi_tab_p.t27 tests=[1] fail=[0] vacuous=[0]
TEST specs/fpga/sar_cmp_qi_unit_probe_ax7203.t27 tests=[1] fail=[0] vacuous=[0]
SEAL specs/fpga/sar_cmp_qi_unit.t27 :: all hashes MATCH
SEAL specs/fpga/sar_cmp_qi_tab_n.t27 :: all hashes MATCH
SEAL specs/fpga/sar_cmp_qi_tab_p.t27 :: all hashes MATCH
SEAL specs/fpga/sar_cmp_qi_unit_probe_ax7203.t27 :: all hashes MATCH
TYPES RATCHET: CLEAN
DUPE failing=1 extra-vs-master=[]
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