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gen-verilog and gen-verilog-hir: hello_world.t27 output is refused by iverilog, verilator and yosys - #6987

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gen-verilog and gen-verilog-hir: hello_world.t27 output is refused by iverilog, verilator and yosys#6987
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  1. Commits on Oct 11, 2026