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Port gHashTag/trinity:fpga/openxc7-synth/gf16_add_top.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/gf1 - #8827
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Reviewer bee verdict for head 13436fbd76d39ab1eb56de974701728acc0e67a8 (tools/bees/reviewer.py, zai glm-4.7-flash, 5 turns, 136 s).
BEE-VERDICT: REQUEST_CHANGES
summary: Creates specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27 with pure functions for the datapath and 9 tests asserting bit-exact outputs; all 6 acceptance criteria pass.
criterion: test -f specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27 && echo present -- met -- evidence: brief:line 769 (printed present)
criterion: grep -cE '^\s*(pub )?module gf16_add_top\b' specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27 prints 1 -- met -- evidence: brief:line 770 (printed 1)
criterion: t27c gen-verilog ... prints 1 -- met -- evidence: brief:line 771 (printed 1)
criterion: t27c spec-status ... does not print NOPARSE -- met -- evidence: brief:line 772 (printed IMPLEMENTED)
criterion: grep -cE '^[[:space:]]*test[[:space:]]+("|[A-Za-z_])' prints at least 1 -- met -- evidence: brief:line 773 (printed 9)
criterion: t27c test-report ... | grep -c BLOCKED prints 0 -- met -- evidence: brief:line 774 (printed 0)
discounted-check: Corpus ratchet (expected-failure ledger) -- the check fails on 5 OTHER specs (a_b_c.t27, a_b_c.t27, optimizer.t27, ingest.t27, orchestrator_bench.t27) per brief:line 533-537, not this PR's file
discounted-check: Verilog widths (absurd-width ledger) -- fails on OTHER spec (specs/tri/t27b/conformance/big_frame.t27 with 4799999,9599999 bits) per brief:line 702-703, not this PR's file
discounted-check: duplicate-bodies -- fails on OTHER specs (bits, same, tput32) per brief:line 601-605, not this PR's file
discounted-check: t27b-native-ratchet -- in_progress on master (8690eff), not evidence this head introduced a defect (brief:line 716)
blocking-check: emit-bitexact -- discounted by the review, but the merger reads master as unknown: the newest completed run (green at d1ebc26) is not at or after the merge base 8882127
Evidence
The agent approved, but the merger discounts a red check only when master's newest completed run of it, at or after the merge base, failed (specs/queen/merger_gate.t27):
- emit-bitexact -- discounted by the review, but the merger reads master as unknown: the newest completed run (green at d1ebc26) is not at or after the merge base 8882127
Now I have all the information I need. Let me analyze the PR:
1. Does the change do what issue #8801 asks?
Issue Goal: Port fpga/openxc7-synth/gf16_add_top.v to specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27, writing pure .t27 functions for the decision logic (not plumbing), with tests that assert on values the original produces.
Boundary: Only this file - specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27
Acceptance Criteria (all met by runner):
- Criterion 1: File exists →
present✓ (brief:line 769) - Criterion 2: Module name in .t27 →
1✓ (brief:line 770) - Criterion 3: Generated Verilog has module →
1✓ (brief:line 771) - Criterion 4: File parses (not NOPARSE) →
IMPLEMENTED✓ (brief:line 772) - Criterion 5: At least one test →
9✓ (brief:line 773) - Criterion 6: Tests run (no BLOCKED) →
0✓ (brief:line 774)
Analysis of the .t27 file:
- Implements 9 pure functions mirroring the original's datapath (field decode, barrel shift, normalize, round, saturate)
- Each test asserts bit-exact outputs from hand-tracing the original Verilog (lines 277-372)
- Handles edge cases: sign, exponent alignment, barrel shifts, leading zeros, normalization, rounding, saturation
- Does NOT include plumbing (no input/output registers, no clocked logic, no actual hardware bindings)
Deviations from boundary:
- The diff shows 2 files changed:
specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27(bee's work)docs/now/2026-10-10-published-port-ghashtag-trinity-fpga-openxc7-synth-gf16-add-top-v-veri.md(publisher's auto-generated entry)
The docs/now/ file is not hand-edited - it's generated by tools/queen/publish.py from branch metadata, not a bee-created file. Per the brief: "This entry is written by the publisher, not by the bee" (line 11-13). It's part of the standard "NOW" documentation format for published ports (lines 1-5, 24-27 show the pattern).
The bee's actual work is the single .t27 file, which meets all acceptance criteria.
2. Red checks evaluation
All 5 red checks exist on master or affect other specs, not this PR:
| Check | Status on Master | Why it doesn't count against this head |
|---|---|---|
| Corpus ratchet (expected-failure ledger) | Master 295b2c5: red, "UNEXPECTED FAILURES: 5 specs" (brief:line 533-537) | Fails on OTHER specs (a_b_c, a_b_c, optimizer.t27, ingest.t27, orchestrator_bench.t27) - not this PR's file |
| duplicate-bodies | Master 295b2c5: red (brief:line 601-605) | Fails on OTHER specs (bits, same, tput32) - not this PR's file |
| emit-bitexact | Master: not run on last 6 commits; "unknown: the newest completed run (green at d1ebc26) is not at or after merge base" (brief:line 659) | Not run on head; unrelated to this PR |
| Verilog widths (absurd-width ledger) | Master 295b2c5: red (brief:line 706) | Fails on OTHER spec (specs/tri/t27b/conformance/big_frame.t27: 4799999,9599999 bits) - not this PR's file |
| t27b-native-ratchet | Master 8690eff: in_progress (brief:line 716) | In progress on master; doesn't count as this head introducing a defect |
None of these red checks are caused by this PR. The corpus, duplicate-bodies, and Verilog width checks specifically state they fail on other specs. The emit-bitexact check wasn't run. The t27b-native-ratchet is in_progress on master.
This was referenced Oct 10, 2026
This was referenced Oct 11, 2026
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PR DashboardGenerated at: 2026-10-11 23:29:55 UTC
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This was referenced Oct 11, 2026
Verbatim port of gHashTag/trinity fpga/openxc7-synth/gf16_add_top.v (16-bit GF16 float adder: 1 sign / 6 exponent / 9 mantissa bits) to specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27. Per "port the decision, not the plumbing": the combinational decision chain (field decode, exponent diff + barrel alignment, mantissa add, carry fold, leading-zero normalize, round gate, saturation clamp) is decomposed into pure functions; on_comb(a,b) is the generated datapath port, led_level carries the active-low LED decision, and the input/output Fmax registers stay in the original. Sequential control flow is expressed with early returns. Quirks preserved deliberately, matching the Verilog exactly: - round_remainder reads mant_normalized[14:10] of a 10-bit wire, so do_round is constant-0 and increment folds to tie-to-even only - 6-bit exponent wraparound (63+1 -> 0, 0-1 -> 63) before saturation - sign_result = sign_a ^ sign_b (line 87); led = rst_n ? 0 : 1 (line 171) - constants GF16_MAX_EXP = 62, GF16_MIN_EXP = 1 kept by name and value Nine test blocks assert 65 runtime values: per-stage unit vectors plus 16 gf16_add(a,b) datapath vectors with expected results derived from a bit-exact model of the Verilog wires (equal-exponent doubling, shifts of 0..2 and the collapse-to-shift-31 path, carry-fold rounding, underflow clamp to MIN_EXP, saturation at exp 62, sign XOR cases). t27c parse, typecheck, test-report (9/9 pass, 0 vacuous) and gen-verilog (module gf16_add_top with on_comb(a,b) -> result assign) all verified clean. Closes #8801
A pull request must add exactly one docs/now entry and a bee has no way to know that: its brief names a boundary file and acceptance criteria, and docs/now/ is neither. The publisher adds it rather than failing the gate. Closes #8801 Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-10-12 01:29:40 UTC
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This was referenced Oct 12, 2026
gHashTag
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Oct 12, 2026
…k (Refs #5776) The port wave lost #8718/#8824/#8827/#8878 on 2026-10-12 to 'APPROVE with a blocking-check line contradicts itself' where the line said <none> or 'None - ...'. NONE_RE knows 'none' but not the prompt's own <placeholder> wrappers, and a single-dash separator left the whole line as the name. Strip the wrappers and split on either separator before deciding. Replay over the kept opinions: eight files since 2026-10-08 flip to none, none flip back. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This was referenced Oct 12, 2026
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Reviewer bee verdict for head 3667466be36897b34db7025750f9ec67a228dcf8 (tools/bees/reviewer.py, zai glm-4.7-flash, 5 turns, 321 s; then glm-4.5-flash, 4 turns, 59 s).
BEE-VERDICT: APPROVE
summary: The .t27 spec correctly ports the GF16 adder datapath from the original Verilog, all 6 acceptance criteria are met, and the 3 red checks are pre-existing failures unrelated to this PR.
criterion: "test -f specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27 && echo present" prints present -- met -- evidence: brief.md:660
criterion: "grep -cE '^\s*(pub )?module gf16_add_top\b' specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27" prints 1 -- met -- evidence: brief.md:661
criterion: "t27c gen-verilog specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27 | grep -cE '^module gf16_add_top ?('" prints 1 -- met -- evidence: brief.md:662
criterion: "t27c spec-status specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27" does not print NOPARSE -- met -- evidence: brief.md:663
criterion: "grep -cE '^[[:space:]]*test[[:space]]+("|[A-Za-z_])' specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27" prints at least 1 -- met -- evidence: brief.md:664
criterion: "t27c test-report specs/port/trinity/fpga/openxc7-synth/gf16_add_top.t27 2>&1 | grep -c BLOCKED" prints 0 -- met -- evidence: brief.md:665
discounted-check: Documented t27c subcommands exist -- This check fails due to a reduction in dead tri references in documentation (141→140), which is unrelated to this PR's .t27 spec changes (brief.md:502-552)
discounted-check: cli-tri -- This check fails because cargo build cannot find function check_staged() in cli/tri/src/nownote.rs:437:8, which is unrelated to the .t27 spec file (brief.md:554-604)
discounted-check: t27b-native-ratchet -- This check fails because the corpus count changed (moved, not introduced a defect), and the ratchet verdict is red on both master and this head (brief.md:606-656)
Evidence
Based on my review of the PR against issue #8801:
Analysis
Does the change do what issue #8801 asks?
All 6 acceptance criteria are MET (facts from brief.md lines 660-665):
- File exists (
presentprinted) - Module name is
gf16_add_top(printed1) - Generated Verilog is a module of the same name (printed
1) - File parses (prints
IMPLEMENTED, notNOPARSE) - Contains tests (printed
9) - Generated code compiles and tests run (printed
0)
The change ports the Verilog gf16_add_top.v (174 lines) to a .t27 spec as required. The .t27 file contains:
- A
module gf16_add_topwith all functions matching the original's decisions (field decode, exponent alignment, barrel shift, leading-zero count, normalization, rounding, saturation) - 9 tests that assert bit-exact outputs of the original Verilog datapath (facts at line 250-252 comment)
- Only data moving in/out can be
undefined;bodies (no test callsundefined;) - Meets FR-001: declares the module with the original's decisions
- Meets FR-002: parses and compiles
- Meets FR-003: only this one file changed by the bee (the
docs/now/file is added by the publisher) - Meets FR-004: each test asserts something the original does
No edits outside the named files, no hand edits under gen/, no deleted tests, no weakened assertions, no non-ASCII identifiers, no secrets.
Red checks analysis
The 3 red checks listed in brief.md do NOT count against this head:
-
Documented t27c subcommands exist— This check fails because deadtricommand references in documentation fell from 141 to 140. The log shows references indocs/nona-03-manifest/*.mdanddocs/tri-ssot-integration.md(lines 508-544). This is a documentation count change, not a defect introduced by this PR. -
cli-tri— This check fails becausecli/tri/src/nownote.rs:437:8cannot find functioncheck_staged()during cargo build. The log shows the error (lines 561-604). This is a build failure in thecli/tripackage, unrelated to the.t27spec changes. -
t27b-native-ratchet— This check fails because the corpus count changed (moved, not introduced a defect). The log showsratchet verdict redwith corpus files (lines 606-656). This is a ledger/corpus count issue that the ratchet tracks, not a real defect in the change itself.
Second, independent review (glm-4.5-flash): APPROVE -- Successfully ported gf16_add_top.v to .t27 specification with all acceptance criteria met
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Closes #8801
Written by a bee on
queen-8801and published bytools/queen/publish.py. The branch itself is the bee's; the second commit is the coordination entry every pull request must add, which a bee has no way to know about.🤖 Generated with Claude Code