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ci(cost-sweep): green on main with no arm ever placed and routed (XDC path + OPAD auto-placement) #896
tnf-cost-sweep.yml has been green on main while no arm was ever placed and routed since the per-arm XDC landed (W928, 8b165f5, 2026-08-19). Green there meant "nothing crashed", not "something was measured".
No Bel named 'OPAD_X0Y11/IOB33/OUTBUF' then Placing design failed
success
Two defects, one behind the other:
Path. The XDC is written to the runner's /tmp/${TOP}.xdc; the container mounts only $PWD:/work, so nextpnr cannot open it.
Pins. With only IOSTANDARD set (the branch above writes the XDC under build/, so it gets past defect 1), nextpnr-xilinx auto-places an output on a GTP pad (OPAD_X0Y11) and placement fails.
Both artefacts carry status=routing-pending, which reads like a fabric limit. Neither run reached the router.
Fix
Branch fix/tnf-cost-sweep-xdc-path:
the XDC lives under build/tnfcost/ (seen as /work/build/tnfcost/);
new tools/sweep_pin_xdc.py gives every port bit a PACKAGE_PIN from the image's own package_pins.csv: general-purpose IOB sites only, clk on an MRCC P pin, bank 34 (the AX7203 DDR3 bank) excluded. Selftest 13/13. On a locally synthesized e3m33 it pins 123 pads with no pin used twice;
an arm whose log never shows Info: Routing.. or Info: Running router2 is recorded as harness-failure and fails the job. Real routing failures stay routing-pending and do not. Negative control: both saved OPAD logs from run 34448747524 contain neither marker (0/0), so they would now fail the job.
Verification run on the branch: to be linked in the PR.
Not measured
Whether the pinned arms route, and at what Fmax -- that is the verification run.
Board behaviour. These pins are not the AX7203's; an Fmax from this workflow compares arms with each other and is never a board number.
Related
Image finding on the same day: eced1cdd (pinned here, W945) predates nextpnr-xilinx 226609704, which disconnects DSP CARRYCASCIN/MULTSIGNIN tied to GND. On gf16_mul, eced1cdd nextpnr fails $PACKER_GND_NET whatever Yosys made the netlist (cross run 37264809032). The _add_top arms are adders; arms that instantiate a DSP multiplier would hit it. Repinning is the owner's call -- see epic: faster FPGA builds through .t27/t27c and by removing CI waste #851.
Run 37266625622 on fix/tnf-cost-sweep-xdc-path (6a9292434, PR #897), image eced1cdd, heap/router1/seed1, target 50 MHz. All five arms were routed on the first attempt. Job success, no harness failure.
arm
E_t
M
PIPELINE
LUT
FF
Fmax
critical path
e4m9
4
9
0
536
18
532.20 MHz *
0.5 ns logic, 1.4 ns routing
e4m11
4
11
0
610
20
372.16 MHz *
0.5 ns logic, 2.2 ns routing
e4m21
4
21
0
1162
30
372.58 MHz *
0.5 ns logic, 2.2 ns routing
e4m29
4
29
1
1634
162
17.93 MHz (fails 50)
11.2 ns logic, 44.5 ns routing
e3m33
3
33
1
1632
170
28.41 MHz (fails 50)
7.1 ns logic, 28.1 ns routing
* PIPELINE=0 arms: the adder datapath runs pad to register and is not timed by the clock Fmax. These three numbers are control-path numbers, not adder numbers. Details are in #898.
The critical-path column is read from the logs in the tnfcost-pnr artifact. The wns field the workflow recorded was empty for every arm; 8d4ba98 on #897 fixes that.
Q1 is answered in this flow. e4m9 536 LUT, e4m11 610 LUT: +74 over two mantissa bits, monotone. e4m9 reproduces exactly across runs 37265666318 and 37266625622: same LUT, FF and Fmax, and the nextpnr logs differ only in wall-clock columns. With a single seed that shows the flow is deterministic. It says nothing about seed spread.
Q2 is not answered.refit.md reports a quadratic with R² = 0.9997 and calls it better than linear. That fit has 5 rows and 4 parameters, and E_t varies in one row only, so e3m33 is fitted exactly and the curve rests on four points with one residual degree of freedom. The two rows past M = 25 are also the only pipelined ones. The refit's verdict text ("flow artefact", "superseded") goes further than this run supports; see #898.
Not measured
Seed spread: one seed per arm.
Whether PIPELINE=1 changes LUT at a fixed M.
Anything on the board. The pins come from the package, not the AX7203 schematic.
Activity
gHashTag commentedon Oct 5, 2026
All five Q1/Q2 arms place and route
Run 37266625622 on
fix/tnf-cost-sweep-xdc-path(6a9292434, PR #897), image eced1cdd,heap/router1/seed1, target 50 MHz. All five arms were routed on the first attempt. Jobsuccess, no harness failure.*
PIPELINE=0arms: the adder datapath runs pad to register and is not timed by the clock Fmax. These three numbers are control-path numbers, not adder numbers. Details are in #898.The critical-path column is read from the logs in the
tnfcost-pnrartifact. Thewnsfield the workflow recorded was empty for every arm; 8d4ba98 on #897 fixes that.Q1 is answered in this flow. e4m9 536 LUT, e4m11 610 LUT: +74 over two mantissa bits, monotone. e4m9 reproduces exactly across runs 37265666318 and 37266625622: same LUT, FF and Fmax, and the nextpnr logs differ only in wall-clock columns. With a single seed that shows the flow is deterministic. It says nothing about seed spread.
Q2 is not answered.
refit.mdreports a quadratic with R² = 0.9997 and calls it better than linear. That fit has 5 rows and 4 parameters, andE_tvaries in one row only, so e3m33 is fitted exactly and the curve rests on four points with one residual degree of freedom. The two rows past M = 25 are also the only pipelined ones. The refit's verdict text ("flow artefact", "superseded") goes further than this run supports; see #898.Not measured
PIPELINE=1changes LUT at a fixed M.🤖 Generated with Claude Code