fix(ci): give fpga-hslm Yosys the embedding_weights.mem it reads

[gHashTag]

What

fpga-hslm-bitstream.yml has failed in Yosys on every run since March:

Can not open file `embedding_weights.mem` for $readmemb.

embedding_lookup.v reads embedding_weights.mem relative to Yosys's working directory,
fpga/openxc7-synth. 6f6840d (2026-03-18) deleted the file there; e8fa551 brought it back
byte-identical (blob 668eaee9), but only as fpga/weights/embedding_weights.mem. This PR copies
it in before synthesis and adds the file and the workflow to the trigger paths.

Measured

run	commit	Yosys	nextpnr
24625363076 (2026-04-19)	main	fails: embedding_weights.mem	not reached
37212434310 (#862 audit dispatch)	main	fails: embedding_weights.mem	not reached
37213637322	15cec09 (this PR)	passes	SA, seed 1: SLICE_LUTX: 48009/126800 37%; 24 min later (15:46:34 → 16:10:58Z) constraint satisfaction check failed … at Bel 'SLICE_X16Y20/C6LUT' and No wire found for port O6

So this PR moves the failure from Yosys to nextpnr; it does not make the job green.

The nextpnr failure is the SA placer bug reported upstream as openXC7/nextpnr-xilinx#162, the same
one #861, #863 and #864 work around with --placer heap. That workaround does not carry over
here. A heap run of this design (37216138482, branch exp/hslm-heap) printed no main-placer
iteration in 3 h 37 min and was cancelled; details are in the comment below.

Not in this PR

• A placer switch: SA hits feat(wave45): Lane MM — wl_boost RTL (OP_WL_BOOST 0xEF, 26/26 PASS) #162 on this design, and heap stalls before its first main-placer iteration.
• The nextpnr step pipes into tee under bash -e without pipefail, so in 37213637322 the step
  went green while nextpnr printed ERROR, and the job failed one step later in fasm2frames. Same
  masking shape ci(fpga): audit the 31 workflows that pass --placer sa against today's image #862 found elsewhere; tracked there, not changed here.

Refs #862

🤖 Generated with Claude Code

[github-actions]

X Brain Health Check

Score: 100.0/100
Status: 🟢 HEALTHY
Threshold: 80/100

X Brain is above merge threshold

[gHashTag]

The heap run: no main-placer iteration in 3 h 37 min

Run 37216138482 (exp/hslm-heap, the same design with --placer heap only) was cancelled at 20:05:54Z, 3 h 37 min into nextpnr. I cancelled it rather than wait for the 360-minute timeout: the account's hosted-runner pool was full (about 200 runs queued across three repos), and the log up to the cancel already answers the question.

The log ends at the start of the main placer:

16:28:24  Creating initial analytic placement for 102579 cells, random placement wirelen = 21885991.
16:28:31  at initial placer iter 0, wirelen = 26378
...
16:28:44  at initial placer iter 3, wirelen = 25793
16:28:44  Running main analytical placer.
20:05:54  ##[error]The operation was canceled.

For comparison, in a completed heap run of a small design (881 cells, nextpnr-control-r1), at iteration #1, type ALL: … follows Running main analytical placer. 0.04 s later, and 22 iterations print in total. Here the four initial iterations took about 4.4 s each, and iteration #1 of the main placer never printed.

So, on this design:

placer	result
SA (37213637322)	fails after 24 min: No wire found for port O6 (openXC7/nextpnr-xilinx#162)
heap (37216138482)	no main-placer iteration in 3 h 37 min; cancelled

The --placer heap workaround that #861, #863 and #864 use does not carry over to fpga-hslm. This PR still moves the failure from Yosys to nextpnr, as the description says. It does not make the job green, and changing the placer would not do that either.

Not measured

• Which phase of iteration deps: bump typescript from 5.9.3 to 6.0.3 in /src/tooling/vscode-vib #1 stalled. The line prints only after solve, spread and legalise have all finished, so the log cannot tell them apart.
• Whether heap would have finished before the 360-minute timeout.
• Any run on a larger runner or on Railway.

[github-actions]

🧪 Brain Stress Test Results

Score: not measured (no stress test prints a Score: line)
Status: 🟢 PASS
Threshold: 270/300

X Stress test passed

[tri-claw]

Summary by t27-bees

This PR fixes a Yosys synthesis failure by copying embedding_weights.mem from fpga/weights/ into the Yosys working directory (fpga/openxc7-synth/) before synthesis. The file was removed from that directory in 2026-03-18 and only restored under fpga/weights/, causing $readmemb to fail.

Worth a look

• .github/workflows/fpga-hslm-bitstream.yml:22-23 — Added trigger paths for the weights file and the workflow itself; correct so changes to the weights or workflow re-run the job.
• .github/workflows/fpga-hslm-bitstream.yml:55-58 — The cp ../weights/embedding_weights.mem . runs in the synthesis step before Yosys; the relative path is correct because the step's working directory is fpga/openxc7-synth/. No obvious breakage risk.

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