Chip tab: signed runs on silicon of the Verilog a spec compiles to, as t27c judged them #1526
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Goal
The Spec Explorer's Chip tab (#955) shows a new, strongest tier of hardware evidence: Verilog compiled from the spec itself, run on a die, with signed receipts judged by t27c run-record.
Where we are
- The Chip tab's silicon history (
src/data/siliconHistory.ts) is hand-transcribed and covers hand-written RTL of the GF formats on the AX7203. It says so. - Since gHashTag/t27 epic #6655 R2/R3,
specs/fpga/ternary_link.t27compiled by t27c ran on a QMTech XC7A200T (verified: the R3-2 live run is citable -- ternary_link re-sealed with built_by, three signed receipts naming die 050d58218fd9854 (Closes #7452) t27#7598): three placements, signed receipts naming the die's DNA, judged complete, FRESH, Die NAMED, citable. - t27c run-record: --receipts <dir> and --json <path>, so the Chip tab shows t27c's own judgment t27#7723 adds
t27c run-record --json, so that judgment exists as data. A follow-up cites the index (docs/reports/silicon-runs/index.json) from a spec, and the existing companion vendoring inscripts/sync-t27-specs.mjsbrings it topublic/t27/files/.
Boundary
apps/website/src/components/SpecSignedRuns.tsx(new, render-only).- Two lines in
apps/website/src/components/SpecChipView.tsx(import, render). - No verdict logic in TypeScript: every verdict word shown is t27c's.
- Owner-approved thin TS glue, 2026-10-08, at most 80 lines.
User Scenarios & Testing
- Given the vendored index lists a run for the selected spec, the Chip tab shows:
- who judged it (
judged_by); - citable or not with the first missing fact;
- authentication, die level and the independence line;
- one row per receipt (seeds, DNA, PASS/FAIL, auth, key, toolchain);
- the exact
t27c run-record ...command to re-check it.
- who judged it (
- Given no index or no run for the spec, nothing renders.
Requirements
- FR-1: every label exists in EN and RU.
- FR-2: a missing or unreadable index renders nothing and throws nothing.
Success Criteria
- The website build and its checks pass in CI.
tsc --noEmitpasses for the new component.
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feat(website): Chip tab shows signed runs on silicon of the Verilog a…
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