[Hahihula]

Adds a sycl feature that runs candle on Intel GPUs via oneAPI DPC++ / Level Zero.

Design

• All SYCL code is behind #[cfg(feature = "sycl")], following the ROCm PR's cfg-gated pattern. Default cargo build is byte-identical and needs no oneAPI toolchain.
• Device kernels live in candle-sycl-kernels (excluded from the workspace). build.rs compiles the csrc/*.cpp SYCL sources into one libcandle_sycl.so via icpx; Rust links it through a flat C ABI. A crate that only depends on this can
  be built by anyone; the kernel crate is the only thing that needs icpx.
• New GPU-free CI job (ci_sycl.yaml) compile-checks the feature + clippy in the intel/oneapi-basekit container.

Coverage

• BackendStorage / BackendDevice full impl: elementwise (19 unary / 6 binary), reductions, cmp, where, gather/scatter/index, sort, pooling, upsample, conv1d/2d + conv_transpose (im2col + oneMKL GEMM), matmul (oneMKL gemm /
  gemm_batch).
• GGUF quantization: GPU dequant for all 12 block types, fused quantized mat-vec (MMVQ) for the decode path, quantize / embedding.
• candle-nn fused ops: native softmax_last_dim, rms_norm, RoPE (3 variants) kernels; sycl_fwd for the rest.
• Allocation pool on the queue; kernels are enqueue-only (sync at host copies / synchronize()).

Status

• On a Meteor Lake Arc iGPU: tensor 35/37, quantized 26/26, matmul / conv / grad / pool / nn ops all green. Only F8E4M3 dtypes unimplemented.
• Qwen3-0.6B Q4_K_M GGUF generates coherent text end-to-end at ~5 tok/s decode (flat with sequence length). Further perf work (MMVQ v2 / DP4a, per-op overhead) is tracked separately.
• CPU path unchanged; no regressions.

proof of actual usability: lucasjinreal/Crane#112