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proof(SafeFPGA): add Proofs.idr — 17 structural invariants, 0 OWED - #34
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…132) `Proven.SafeFPGA` claimed "Invalid configurations are caught at validation time rather than during synthesis or at hardware programming time" but shipped no `Proofs.idr` — one of the ~30 named gaps under standards#132. This commit lands `src/Proven/SafeFPGA/Proofs.idr` with 17 machine-checked theorems. Zero believe_me, zero idris_crash, zero OWED postulates — every claim is type-level reducible. DISCHARGED (idris2 --check exit 0): Enum self-equality (6 + 5 = 11 cases): xilinx7SelfEq, ultraScaleSelfEq, versalSelfEq, cycloneVSelfEq, agilexSelfEq, latticeSelfEq (FPGAFamily) lutSelfEq, ffSelfEq, bramSelfEq, dspSelfEq, ioSelfEq (ResourceType) xilinx7VsVersalNotEq (cross-pair anchor) Resource-budget boundary (3): zeroUtilWithinBudget : 0% utilisation passes fullUtilWithinBudget : 100% utilisation passes (max-allowed) overUtilNotWithinBudget : 101% utilisation fails Bitstream-validator soundness (1): validateBitstreamPreservesConfig — `validateBitstream cfg = Just cfg' -> cfg' = cfg` (no silent mutation, clamping, or coercion of fields) Routing-congestion identity (1): emptyBudgetZeroCongestion : empty resource budget -> 0 congestion Timing-likely thresholds (2): emptyBudgetLowClockMeetsTiming : 500 MHz + empty -> True emptyBudgetHighClockMeetsTiming : 600 MHz + empty -> True Note: `IO` as a constructor of `ResourceType` is shadowed by `PrimIO.IO`, so `ioSelfEq` is qualified as `Proven.SafeFPGA.IO == Proven.SafeFPGA.IO`. This is a real ambiguity in the module's API that should be flagged for a future rename (e.g. `IOPin`). Verified locally: $ idris2 --check src/Proven/SafeFPGA/Proofs.idr 1/2: Building Proven.SafeFPGA 2/2: Building Proven.SafeFPGA.Proofs rc: 0 This closes one more of the ~30 named "no Proofs.idr" gaps under #132 — and this one cleanly, with no OWED debt. Refs metadatastician/standards#124, metadatastician/standards#132. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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| -- SPDX-License-Identifier: PMPL-1.0-or-later | |||
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Summary
`Proven.SafeFPGA` claimed "Invalid configurations are caught at validation time rather than during synthesis or at hardware programming time" but shipped no `Proofs.idr` — one of the ~30 named gaps under standards#132. This PR lands `src/Proven/SafeFPGA/Proofs.idr` with 17 machine-checked theorems and ZERO OWED postulates — every claim is type-level reducible.
Discharged (17)
Zero `believe_me`, zero `idris_crash`, zero OWED.
Note: latent API ambiguity flagged
`IO` as a constructor of `ResourceType` shadows `PrimIO.IO`, so `ioSelfEq` had to be qualified as `Proven.SafeFPGA.IO == Proven.SafeFPGA.IO`. This is a real ambiguity in the module's API and should be flagged for a future rename (e.g. `IOPin`).
Verification
```
$ idris2 --check src/Proven/SafeFPGA/Proofs.idr
1/2: Building Proven.SafeFPGA
2/2: Building Proven.SafeFPGA.Proofs
rc: 0
```
Refs
🤖 Generated with Claude Code