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Derive the timer interrupt context index from the timer table #11901

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8 changes: 8 additions & 0 deletions src/main/drivers/timer.h
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Original file line number Diff line number Diff line change
Expand Up @@ -55,14 +55,22 @@ typedef uint32_t timCNT_t;
#error "Unknown CPU defined"
#endif

// TIMER_INDEX() maps a hardware timer number to its slot in timerDefinitions[] and
// timerCtx[]. This is not always (n - 1): the tables are packed and not every MCU has
// a contiguous range of timers (STM32H7 has no TIM9..TIM11, AT32F43x adds TMR20 after
// TMR14). Timer tables and timer IRQ handlers must use this macro.
#if defined(STM32F4)
#define HARDWARE_TIMER_DEFINITION_COUNT 14
#define TIMER_INDEX(n) ((n) - 1) // TIM1..TIM14
#elif defined(STM32F7)
#define HARDWARE_TIMER_DEFINITION_COUNT 14
#define TIMER_INDEX(n) ((n) - 1) // TIM1..TIM14
#elif defined(STM32H7)
#define HARDWARE_TIMER_DEFINITION_COUNT 14
#define TIMER_INDEX(n) ((n) < 9 ? (n) - 1 : (n) - 4) // TIM1..TIM8, TIM12..TIM17
#elif defined(AT32F43x)
#define HARDWARE_TIMER_DEFINITION_COUNT 15
#define TIMER_INDEX(n) ((n) < 20 ? (n) - 1 : 14) // TMR1..TMR14, TMR20
#elif defined(SITL_BUILD)
#define HARDWARE_TIMER_DEFINITION_COUNT 0
#elif defined(RP2350)
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33 changes: 18 additions & 15 deletions src/main/drivers/timer_at32f43x.c
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Expand Up @@ -34,66 +34,69 @@

const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
#if defined(TMR1)
[0] = { .tim = TMR1, .rcc = RCC_APB2(TMR1), .irq = TMR1_CH_IRQn, .secondIrq = TMR1_OVF_TMR10_IRQn },
[TIMER_INDEX(1)] = { .tim = TMR1, .rcc = RCC_APB2(TMR1), .irq = TMR1_CH_IRQn, .secondIrq = TMR1_OVF_TMR10_IRQn },
#endif

#if defined(TMR2)
[1] = { .tim = TMR2, .rcc = RCC_APB1(TMR2), .irq = TMR2_GLOBAL_IRQn},
[TIMER_INDEX(2)] = { .tim = TMR2, .rcc = RCC_APB1(TMR2), .irq = TMR2_GLOBAL_IRQn},
#endif

#if defined(TMR3)
[2] = { .tim = TMR3, .rcc = RCC_APB1(TMR3), .irq = TMR3_GLOBAL_IRQn},
[TIMER_INDEX(3)] = { .tim = TMR3, .rcc = RCC_APB1(TMR3), .irq = TMR3_GLOBAL_IRQn},
#endif

#if defined(TMR4)
[3] = { .tim = TMR4, .rcc = RCC_APB1(TMR4), .irq = TMR4_GLOBAL_IRQn},
[TIMER_INDEX(4)] = { .tim = TMR4, .rcc = RCC_APB1(TMR4), .irq = TMR4_GLOBAL_IRQn},
#endif

#if defined(TMR5)
[4] = { .tim = TMR5, .rcc = RCC_APB1(TMR5), .irq = TMR5_GLOBAL_IRQn},
[TIMER_INDEX(5)] = { .tim = TMR5, .rcc = RCC_APB1(TMR5), .irq = TMR5_GLOBAL_IRQn},
#endif

#if defined(TMR6)
[5] = { .tim = TMR6, .rcc = RCC_APB1(TMR6), .irq = 0},
[TIMER_INDEX(6)] = { .tim = TMR6, .rcc = RCC_APB1(TMR6), .irq = 0},
#endif

#if defined(TMR7)
[6] = { .tim = TMR7, .rcc = RCC_APB1(TMR7), .irq = 0},
[TIMER_INDEX(7)] = { .tim = TMR7, .rcc = RCC_APB1(TMR7), .irq = 0},
#endif

#if defined(TMR8)
[7] = { .tim = TMR8, .rcc = RCC_APB2(TMR8), .irq = TMR8_CH_IRQn, .secondIrq = TMR8_OVF_TMR13_IRQn },
[TIMER_INDEX(8)] = { .tim = TMR8, .rcc = RCC_APB2(TMR8), .irq = TMR8_CH_IRQn, .secondIrq = TMR8_OVF_TMR13_IRQn },
#endif

#if defined(TMR9)
[8] = { .tim = TMR9, .rcc = RCC_APB2(TMR9), .irq = TMR1_BRK_TMR9_IRQn},
[TIMER_INDEX(9)] = { .tim = TMR9, .rcc = RCC_APB2(TMR9), .irq = TMR1_BRK_TMR9_IRQn},
#endif

#if defined(TMR10)
[9] = { .tim = TMR10, .rcc = RCC_APB2(TMR10), .irq = TMR1_OVF_TMR10_IRQn},
[TIMER_INDEX(10)] = { .tim = TMR10, .rcc = RCC_APB2(TMR10), .irq = TMR1_OVF_TMR10_IRQn},
#endif

#if defined(TMR11)
[10] = { .tim = TMR11, .rcc = RCC_APB2(TMR11), .irq = TMR1_TRG_HALL_TMR11_IRQn},
[TIMER_INDEX(11)] = { .tim = TMR11, .rcc = RCC_APB2(TMR11), .irq = TMR1_TRG_HALL_TMR11_IRQn},
#endif

#if defined(TMR12)
[11] = { .tim = TMR12, .rcc = RCC_APB1(TMR12), .irq = TMR8_BRK_TMR12_IRQn},
[TIMER_INDEX(12)] = { .tim = TMR12, .rcc = RCC_APB1(TMR12), .irq = TMR8_BRK_TMR12_IRQn},
#endif

#if defined(TMR13)
[12] = { .tim = TMR13, .rcc = RCC_APB1(TMR13), .irq = TMR8_OVF_TMR13_IRQn},
[TIMER_INDEX(13)] = { .tim = TMR13, .rcc = RCC_APB1(TMR13), .irq = TMR8_OVF_TMR13_IRQn},
#endif

#if defined(TMR14)
[13] = { .tim = TMR14, .rcc = RCC_APB1(TMR14), .irq = TMR8_TRG_HALL_TMR14_IRQn},
[TIMER_INDEX(14)] = { .tim = TMR14, .rcc = RCC_APB1(TMR14), .irq = TMR8_TRG_HALL_TMR14_IRQn},
#endif

#if defined(TMR20)
[14] = { .tim = TMR20, .rcc = RCC_APB2(TMR20), .irq = TMR20_CH_IRQn},
[TIMER_INDEX(20)] = { .tim = TMR20, .rcc = RCC_APB2(TMR20), .irq = TMR20_CH_IRQn},
#endif
};

// The timer table must cover every slot of timerCtx[] - see TIMER_INDEX() in timer.h
STATIC_ASSERT(TIMER_INDEX(20) == HARDWARE_TIMER_DEFINITION_COUNT - 1, timer_definition_table_size_mismatch);

uint32_t timerClock(tmr_type *tim)
{
UNUSED(tim);
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24 changes: 18 additions & 6 deletions src/main/drivers/timer_impl.h
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Expand Up @@ -17,22 +17,29 @@

#pragma once

#include "common/utils.h"

#if defined(AT32F43x)
#define IMPL_TIM_IT_UPDATE_INTERRUPT TMR_OVF_INT
#define TIM_IT_CCx(chIdx) (TMR_C1_INT << (chIdx))
// 0x2 0x4 0x8 0x10 0\1\2\3

#define _TIM_IRQ_HANDLER2(name, i, j) \
STATIC_ASSERT(TIMER_INDEX(i) < HARDWARE_TIMER_DEFINITION_COUNT && \
TIMER_INDEX(j) < HARDWARE_TIMER_DEFINITION_COUNT, \
name ## _timer_index_out_of_range); \
void name(void) \
{ \
impl_timerCaptureCompareHandler(TMR ## i, timerCtx[i - 1]); \
impl_timerCaptureCompareHandler(TMR ## j, timerCtx[j - 1]); \
impl_timerCaptureCompareHandler(TMR ## i, timerCtx[TIMER_INDEX(i)]); \
impl_timerCaptureCompareHandler(TMR ## j, timerCtx[TIMER_INDEX(j)]); \
} struct dummy

#define _TIM_IRQ_HANDLER(name, i) \
STATIC_ASSERT(TIMER_INDEX(i) < HARDWARE_TIMER_DEFINITION_COUNT, \
name ## _timer_index_out_of_range); \
void name(void) \
{ \
impl_timerCaptureCompareHandler(TMR ## i, timerCtx[i - 1]); \
impl_timerCaptureCompareHandler(TMR ## i, timerCtx[TIMER_INDEX(i)]); \
} struct dummy

uint8_t lookupTimerIndex(const tmr_type *tim);
Expand All @@ -49,16 +56,21 @@ void impl_timerCaptureCompareHandler(tmr_type *tim, timHardwareContext_t * timer
#endif

#define _TIM_IRQ_HANDLER2(name, i, j) \
STATIC_ASSERT(TIMER_INDEX(i) < HARDWARE_TIMER_DEFINITION_COUNT && \
TIMER_INDEX(j) < HARDWARE_TIMER_DEFINITION_COUNT, \
name ## _timer_index_out_of_range); \
void name(void) \
{ \
impl_timerCaptureCompareHandler(TIM ## i, timerCtx[i - 1]); \
impl_timerCaptureCompareHandler(TIM ## j, timerCtx[j - 1]); \
impl_timerCaptureCompareHandler(TIM ## i, timerCtx[TIMER_INDEX(i)]); \
impl_timerCaptureCompareHandler(TIM ## j, timerCtx[TIMER_INDEX(j)]); \
} struct dummy

#define _TIM_IRQ_HANDLER(name, i) \
STATIC_ASSERT(TIMER_INDEX(i) < HARDWARE_TIMER_DEFINITION_COUNT, \
name ## _timer_index_out_of_range); \
void name(void) \
{ \
impl_timerCaptureCompareHandler(TIM ## i, timerCtx[i - 1]); \
impl_timerCaptureCompareHandler(TIM ## i, timerCtx[TIMER_INDEX(i)]); \
} struct dummy

uint8_t lookupTimerIndex(const TIM_TypeDef *tim);
Expand Down
33 changes: 18 additions & 15 deletions src/main/drivers/timer_stm32f4xx.c
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Expand Up @@ -35,66 +35,69 @@

const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
#if defined(TIM1)
[0] = { .tim = TIM1, .rcc = RCC_APB2(TIM1), .irq = TIM1_CC_IRQn, .secondIrq = TIM1_UP_TIM10_IRQn },
[TIMER_INDEX(1)] = { .tim = TIM1, .rcc = RCC_APB2(TIM1), .irq = TIM1_CC_IRQn, .secondIrq = TIM1_UP_TIM10_IRQn },
#endif

#if defined(TIM2)
[1] = { .tim = TIM2, .rcc = RCC_APB1(TIM2), .irq = TIM2_IRQn},
[TIMER_INDEX(2)] = { .tim = TIM2, .rcc = RCC_APB1(TIM2), .irq = TIM2_IRQn},
#endif

#if defined(TIM3)
[2] = { .tim = TIM3, .rcc = RCC_APB1(TIM3), .irq = TIM3_IRQn},
[TIMER_INDEX(3)] = { .tim = TIM3, .rcc = RCC_APB1(TIM3), .irq = TIM3_IRQn},
#endif

#if defined(TIM4)
[3] = { .tim = TIM4, .rcc = RCC_APB1(TIM4), .irq = TIM4_IRQn},
[TIMER_INDEX(4)] = { .tim = TIM4, .rcc = RCC_APB1(TIM4), .irq = TIM4_IRQn},
#endif

#if defined(TIM5)
[4] = { .tim = TIM5, .rcc = RCC_APB1(TIM5), .irq = TIM5_IRQn},
[TIMER_INDEX(5)] = { .tim = TIM5, .rcc = RCC_APB1(TIM5), .irq = TIM5_IRQn},
#endif

#if defined(TIM6)
[5] = { .tim = TIM6, .rcc = RCC_APB1(TIM6), .irq = 0},
[TIMER_INDEX(6)] = { .tim = TIM6, .rcc = RCC_APB1(TIM6), .irq = 0},
#endif

#if defined(TIM7)
[6] = { .tim = TIM7, .rcc = RCC_APB1(TIM7), .irq = 0},
[TIMER_INDEX(7)] = { .tim = TIM7, .rcc = RCC_APB1(TIM7), .irq = 0},
#endif

#if defined(TIM8) && !defined(STM32F411xE)
#if defined(STM32F446xx)
[7] = { .tim = TIM8, .rcc = RCC_APB2(TIM8), .irq = 0 },
[TIMER_INDEX(8)] = { .tim = TIM8, .rcc = RCC_APB2(TIM8), .irq = 0 },
#else
[7] = { .tim = TIM8, .rcc = RCC_APB2(TIM8), .irq = TIM8_CC_IRQn, .secondIrq = TIM8_UP_TIM13_IRQn },
[TIMER_INDEX(8)] = { .tim = TIM8, .rcc = RCC_APB2(TIM8), .irq = TIM8_CC_IRQn, .secondIrq = TIM8_UP_TIM13_IRQn },
#endif
#endif

#if defined(TIM9)
[8] = { .tim = TIM9, .rcc = RCC_APB2(TIM9), .irq = TIM1_BRK_TIM9_IRQn},
[TIMER_INDEX(9)] = { .tim = TIM9, .rcc = RCC_APB2(TIM9), .irq = TIM1_BRK_TIM9_IRQn},
#endif

#if defined(TIM10)
[9] = { .tim = TIM10, .rcc = RCC_APB2(TIM10), .irq = TIM1_UP_TIM10_IRQn},
[TIMER_INDEX(10)] = { .tim = TIM10, .rcc = RCC_APB2(TIM10), .irq = TIM1_UP_TIM10_IRQn},
#endif

#if defined(TIM11)
[10] = { .tim = TIM11, .rcc = RCC_APB2(TIM11), .irq = TIM1_TRG_COM_TIM11_IRQn},
[TIMER_INDEX(11)] = { .tim = TIM11, .rcc = RCC_APB2(TIM11), .irq = TIM1_TRG_COM_TIM11_IRQn},
#endif

#if defined(TIM12) && !defined(STM32F411xE)
[11] = { .tim = TIM12, .rcc = RCC_APB1(TIM12), .irq = TIM8_BRK_TIM12_IRQn},
[TIMER_INDEX(12)] = { .tim = TIM12, .rcc = RCC_APB1(TIM12), .irq = TIM8_BRK_TIM12_IRQn},
#endif

#if defined(TIM13) && !defined(STM32F411xE)
[12] = { .tim = TIM13, .rcc = RCC_APB1(TIM13), .irq = TIM8_UP_TIM13_IRQn},
[TIMER_INDEX(13)] = { .tim = TIM13, .rcc = RCC_APB1(TIM13), .irq = TIM8_UP_TIM13_IRQn},
#endif

#if defined(TIM14) && !defined(STM32F411xE)
[13] = { .tim = TIM14, .rcc = RCC_APB1(TIM14), .irq = TIM8_TRG_COM_TIM14_IRQn},
[TIMER_INDEX(14)] = { .tim = TIM14, .rcc = RCC_APB1(TIM14), .irq = TIM8_TRG_COM_TIM14_IRQn},
#endif
};

// The timer table must cover every slot of timerCtx[] - see TIMER_INDEX() in timer.h
STATIC_ASSERT(TIMER_INDEX(14) == HARDWARE_TIMER_DEFINITION_COUNT - 1, timer_definition_table_size_mismatch);

uint32_t timerClock(TIM_TypeDef *tim)
{
#if defined (STM32F411xE)
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31 changes: 17 additions & 14 deletions src/main/drivers/timer_stm32f7xx.c
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Expand Up @@ -32,22 +32,25 @@
#include "stm32f7xx.h"

const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
[0] = { .tim = TIM1, .rcc = RCC_APB2(TIM1), .irq = TIM1_CC_IRQn, .secondIrq = TIM1_UP_TIM10_IRQn },
[1] = { .tim = TIM2, .rcc = RCC_APB1(TIM2), .irq = TIM2_IRQn},
[2] = { .tim = TIM3, .rcc = RCC_APB1(TIM3), .irq = TIM3_IRQn},
[3] = { .tim = TIM4, .rcc = RCC_APB1(TIM4), .irq = TIM4_IRQn},
[4] = { .tim = TIM5, .rcc = RCC_APB1(TIM5), .irq = TIM5_IRQn},
[5] = { .tim = TIM6, .rcc = RCC_APB1(TIM6), .irq = 0},
[6] = { .tim = TIM7, .rcc = RCC_APB1(TIM7), .irq = 0},
[7] = { .tim = TIM8, .rcc = RCC_APB2(TIM8), .irq = TIM8_CC_IRQn, .secondIrq = TIM8_UP_TIM13_IRQn},
[8] = { .tim = TIM9, .rcc = RCC_APB2(TIM9), .irq = TIM1_BRK_TIM9_IRQn},
[9] = { .tim = TIM10, .rcc = RCC_APB2(TIM10), .irq = TIM1_UP_TIM10_IRQn},
[10] = { .tim = TIM11, .rcc = RCC_APB2(TIM11), .irq = TIM1_TRG_COM_TIM11_IRQn},
[11] = { .tim = TIM12, .rcc = RCC_APB1(TIM12), .irq = TIM8_BRK_TIM12_IRQn},
[12] = { .tim = TIM13, .rcc = RCC_APB1(TIM13), .irq = TIM8_UP_TIM13_IRQn},
[13] = { .tim = TIM14, .rcc = RCC_APB1(TIM14), .irq = TIM8_TRG_COM_TIM14_IRQn},
[TIMER_INDEX(1)] = { .tim = TIM1, .rcc = RCC_APB2(TIM1), .irq = TIM1_CC_IRQn, .secondIrq = TIM1_UP_TIM10_IRQn },
[TIMER_INDEX(2)] = { .tim = TIM2, .rcc = RCC_APB1(TIM2), .irq = TIM2_IRQn},
[TIMER_INDEX(3)] = { .tim = TIM3, .rcc = RCC_APB1(TIM3), .irq = TIM3_IRQn},
[TIMER_INDEX(4)] = { .tim = TIM4, .rcc = RCC_APB1(TIM4), .irq = TIM4_IRQn},
[TIMER_INDEX(5)] = { .tim = TIM5, .rcc = RCC_APB1(TIM5), .irq = TIM5_IRQn},
[TIMER_INDEX(6)] = { .tim = TIM6, .rcc = RCC_APB1(TIM6), .irq = 0},
[TIMER_INDEX(7)] = { .tim = TIM7, .rcc = RCC_APB1(TIM7), .irq = 0},
[TIMER_INDEX(8)] = { .tim = TIM8, .rcc = RCC_APB2(TIM8), .irq = TIM8_CC_IRQn, .secondIrq = TIM8_UP_TIM13_IRQn},
[TIMER_INDEX(9)] = { .tim = TIM9, .rcc = RCC_APB2(TIM9), .irq = TIM1_BRK_TIM9_IRQn},
[TIMER_INDEX(10)] = { .tim = TIM10, .rcc = RCC_APB2(TIM10), .irq = TIM1_UP_TIM10_IRQn},
[TIMER_INDEX(11)] = { .tim = TIM11, .rcc = RCC_APB2(TIM11), .irq = TIM1_TRG_COM_TIM11_IRQn},
[TIMER_INDEX(12)] = { .tim = TIM12, .rcc = RCC_APB1(TIM12), .irq = TIM8_BRK_TIM12_IRQn},
[TIMER_INDEX(13)] = { .tim = TIM13, .rcc = RCC_APB1(TIM13), .irq = TIM8_UP_TIM13_IRQn},
[TIMER_INDEX(14)] = { .tim = TIM14, .rcc = RCC_APB1(TIM14), .irq = TIM8_TRG_COM_TIM14_IRQn},
};

// The timer table must cover every slot of timerCtx[] - see TIMER_INDEX() in timer.h
STATIC_ASSERT(TIMER_INDEX(14) == HARDWARE_TIMER_DEFINITION_COUNT - 1, timer_definition_table_size_mismatch);

uint32_t timerClock(TIM_TypeDef *tim)
{
UNUSED(tim);
Expand Down
31 changes: 17 additions & 14 deletions src/main/drivers/timer_stm32h7xx.c
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Expand Up @@ -32,22 +32,25 @@
#include "stm32h7xx.h"

const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
[0] = { .tim = TIM1, .rcc = RCC_APB2(TIM1), .irq = TIM1_CC_IRQn},
[1] = { .tim = TIM2, .rcc = RCC_APB1L(TIM2), .irq = TIM2_IRQn},
[2] = { .tim = TIM3, .rcc = RCC_APB1L(TIM3), .irq = TIM3_IRQn},
[3] = { .tim = TIM4, .rcc = RCC_APB1L(TIM4), .irq = TIM4_IRQn},
[4] = { .tim = TIM5, .rcc = RCC_APB1L(TIM5), .irq = TIM5_IRQn},
[5] = { .tim = TIM6, .rcc = RCC_APB1L(TIM6), .irq = 0},
[6] = { .tim = TIM7, .rcc = RCC_APB1L(TIM7), .irq = 0},
[7] = { .tim = TIM8, .rcc = RCC_APB2(TIM8), .irq = TIM8_CC_IRQn},
[8] = { .tim = TIM12, .rcc = RCC_APB1L(TIM12), .irq = TIM8_BRK_TIM12_IRQn},
[9] = { .tim = TIM13, .rcc = RCC_APB1L(TIM13), .irq = TIM8_UP_TIM13_IRQn},
[10] = { .tim = TIM14, .rcc = RCC_APB1L(TIM14), .irq = TIM8_TRG_COM_TIM14_IRQn},
[11] = { .tim = TIM15, .rcc = RCC_APB2(TIM15), .irq = TIM15_IRQn},
[12] = { .tim = TIM16, .rcc = RCC_APB2(TIM16), .irq = TIM16_IRQn},
[13] = { .tim = TIM17, .rcc = RCC_APB2(TIM17), .irq = TIM17_IRQn},
[TIMER_INDEX(1)] = { .tim = TIM1, .rcc = RCC_APB2(TIM1), .irq = TIM1_CC_IRQn},
[TIMER_INDEX(2)] = { .tim = TIM2, .rcc = RCC_APB1L(TIM2), .irq = TIM2_IRQn},
[TIMER_INDEX(3)] = { .tim = TIM3, .rcc = RCC_APB1L(TIM3), .irq = TIM3_IRQn},
[TIMER_INDEX(4)] = { .tim = TIM4, .rcc = RCC_APB1L(TIM4), .irq = TIM4_IRQn},
[TIMER_INDEX(5)] = { .tim = TIM5, .rcc = RCC_APB1L(TIM5), .irq = TIM5_IRQn},
[TIMER_INDEX(6)] = { .tim = TIM6, .rcc = RCC_APB1L(TIM6), .irq = 0},
[TIMER_INDEX(7)] = { .tim = TIM7, .rcc = RCC_APB1L(TIM7), .irq = 0},
[TIMER_INDEX(8)] = { .tim = TIM8, .rcc = RCC_APB2(TIM8), .irq = TIM8_CC_IRQn},
[TIMER_INDEX(12)] = { .tim = TIM12, .rcc = RCC_APB1L(TIM12), .irq = TIM8_BRK_TIM12_IRQn},
[TIMER_INDEX(13)] = { .tim = TIM13, .rcc = RCC_APB1L(TIM13), .irq = TIM8_UP_TIM13_IRQn},
[TIMER_INDEX(14)] = { .tim = TIM14, .rcc = RCC_APB1L(TIM14), .irq = TIM8_TRG_COM_TIM14_IRQn},
[TIMER_INDEX(15)] = { .tim = TIM15, .rcc = RCC_APB2(TIM15), .irq = TIM15_IRQn},
[TIMER_INDEX(16)] = { .tim = TIM16, .rcc = RCC_APB2(TIM16), .irq = TIM16_IRQn},
[TIMER_INDEX(17)] = { .tim = TIM17, .rcc = RCC_APB2(TIM17), .irq = TIM17_IRQn},
};

// The timer table must cover every slot of timerCtx[] - see TIMER_INDEX() in timer.h
STATIC_ASSERT(TIMER_INDEX(17) == HARDWARE_TIMER_DEFINITION_COUNT - 1, timer_definition_table_size_mismatch);

uint32_t timerClock(TIM_TypeDef *tim)
{
int timpre;
Expand Down
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