Send the full page address on 2Gbit W25N devices

[Raffi1202]

Problem

#11376 reports that on a RADIOLINKF405 flash_erase prints "Done" and flash_info shows usedSize=0, but after a power cycle the old usedSize is back. That board has a 1 Gbit W25N01GV. While reading the driver for that report, a second defect turned up that affects only the 2 Gbit parts served by the same driver (W25N02KV on NEXUSX and ORBITH743, MX35LF2G): bit 16 of the page address is never sent, so every read, program and erase aimed at the upper 128 MB lands in the lower half. This PR fixes that defect only; the bytes sent to a W25N01GV are unchanged, so it does not close #11376.

Cause

src/main/drivers/flash_w25n.c:163 on maintenance-10.x: w25n_performCommandWithPageAddress() sends { command, 0, pageAddress >> 8, pageAddress }, a fixed zero followed by 16 address bits. The W25N01GV has 1024 blocks x 64 pages = 65536 pages (:38), which fits; the W25N02KV and MX35LF2G have 2048 blocks (:39-40), so page addresses reach 131071 and bit 16 is lost. All three callers go through this helper: block erase (:305), program execute (:345), page data read (:494). FLASHFS spans every sector (src/main/drivers/flash.c:217), so addresses above 128 MB are reached in normal logging.

Change

The first address byte now carries bits 23..16 of the page address instead of a constant zero, with a comment explaining why. On the W25N01GV those bits are zero for every valid page, so its wire sequence is byte-for-byte unchanged. No die select is added: the driver's geometry gives 2048 blocks per die for both 2 Gbit parts.

Test

Not run on hardware, and no CI run exists for this branch yet. Cause verified by reading flash_w25n.c:163 and the geometry table at :237-274 on maintenance-10.x. The byte layout matches Betaflight's driver, which sends (pageAddress >> 16) & 0xff in the same position: https://github.com/betaflight/betaflight/blob/master/src/main/drivers/flash/flash_w25n.c. Qodo review on 31d637f: 0 bugs.

Flash / RAM

Not measured yet. The upstream firmware CI has not been released for this PR, so no size report exists.

Docs

No documentation change needed: docs/Blackbox.md:125 and docs/development/targets/common-issues.md:361 already list the W25N02 as a 2 Gbit / 256 MB chip; the driver now matches that.

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PR Summary by Qodo

Send full page addresses to 2 Gbit W25N flash devices

🐞 Bug fix 🕐 10-20 Minutes

AI Description

• Preserve page-address bit 16 when commanding 2 Gbit W25N-compatible NAND devices.
• Prevent upper-half reads, programs, and erases from targeting lower-half pages.
• Keep command bytes unchanged for valid 1 Gbit device addresses.

Diagram

sequenceDiagram
    participant Ops as Flash Operations
    participant Addr as Address Command
    participant Bus as SPI Bus
    participant NAND as W25N Device
    Ops->>Addr: Read program or erase page
    Addr->>Addr: Encode bits 23 through 0
    Addr->>Bus: Send command and address
    Bus->>NAND: Transfer full page address
    NAND-->>Ops: Access intended page

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High-Level Assessment

Serializing bits 23 through 16 in the existing three-byte address field is the protocol-correct and simplest approach. Conditional encoding by device geometry was considered unnecessary because valid W25N01GV addresses naturally leave the added byte zero, preserving its existing wire sequence.

Files changed (1) +4 / -1

Bug fix (1) +4 / -1

flash_w25n.cSerialize the complete NAND page address +4/-1

Serialize the complete NAND page address

• The shared page-address command helper now places bits 23 through 16 into the first address byte instead of always sending zero. This fixes page reads, program execution, and block erasure in the upper half of supported 2 Gbit devices while leaving valid W25N01GV commands unchanged.

src/main/drivers/flash_w25n.c

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Code Review by Qodo

🐞 Bugs (0) 📘 Rule violations (0) 📎 Requirement gaps (0)

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