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jon merged 1 commit into from
Sep 28, 2026
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Support Cortex-M33 acquisition and halt/resume. #78

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6 changes: 3 additions & 3 deletions README.md
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Expand Up @@ -69,9 +69,9 @@ The [examples](examples) begin with a raw SWD debug-port identity read, then add
posted access-port reads and a Cortex-M identity read through a MEM-AP. They
compose the public packages explicitly without duplicating their framing. The
`target/cortexm` package reads and decodes the architectural CPUID value through
any compatible target-word reader. It also provides acquired Cortex-M0
halt/resume control, stepping, and halted register access over word memory; see
[Cortex-M control](docs/cortexm.md).
any compatible target-word reader. It also provides acquired Cortex-M0 and
Cortex-M33 halt/resume control over word memory, plus Cortex-M0 stepping and
halted register access; see [Cortex-M control](docs/cortexm.md).

The FTDI path uses the standard H-series MPSSE port and endpoint layout.
Descriptor-driven FTDI port binding is not implemented yet. J-Link instead
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21 changes: 11 additions & 10 deletions docs/architecture.md
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Expand Up @@ -23,7 +23,7 @@ USB host access
Arm Debug Port and MEM-AP
|
v
Cortex-M identity and Cortex-M0 control
Cortex-M identity and Cortex-M0/M33 control
|
v
examples and ost
Expand Down Expand Up @@ -51,7 +51,7 @@ service.
| `dap` | Bind SW-DP or baseline ADIv5 JTAG-DP, manage identity and power, execute ordered DP/AP transactions, and provide scalar or block MEM-AP access. |
| `dap/sim` | Model the DP, AP, and byte-addressed target-memory state consumed by `dap`. |
| `coresight` | Identify debug components and walk ROM tables through borrowed scalar memory, with explicit bounds and no resource acquisition or target-memory writes. |
| `target/cortexm` | Identify Cortex-M processors and own Cortex-M0 halting debug and register access over borrowed word memory. |
| `target/cortexm` | Identify Cortex-M processors and own Cortex-M0/M33 halting debug, with Cortex-M0 register access, over borrowed word memory. |
| `examples/...` | Demonstrate public package compositions as executable programs. |
| `cmd/ost` | Provide a small command hierarchy over the same public packages. |

Expand Down Expand Up @@ -326,14 +326,15 @@ transfer sizes but owns no DAP or MEM-AP state. See
[CoreSight component identity](coresight.md) for its register and failure
boundaries.

`target/cortexm` identifies processors through a word reader. Cortex-M0 control
also requires a word writer that waits for each access to complete. The target
owns DHCSR control, its halt requests, and pending register and step operations.
Stepping checks DFSR to preserve competing stops. Release settles pending
operations before restoring debug control; the target must be released before
the memory owner. Register writes persist after release. It does not know about
USB, adapters, or wire protocols. See [Cortex-M control](cortexm.md) for
restoration and failure boundaries.
`target/cortexm` identifies processors through a word reader. Cortex-M0/M33
control also requires a word writer that waits for each access to complete. The
target owns DHCSR control, its halt requests, and pending register and step
operations. Stepping checks DFSR to preserve competing stops. Release settles
pending operations before restoring debug control; the target must be released
before the memory owner. Register writes persist after release. It does not know
about USB, adapters, or wire protocols. See [Cortex-M control](cortexm.md) for
restoration and failure boundaries. Cortex-M33 control requires Secure invasive
debug permission and excludes register access and stepping.

## Host implementations

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31 changes: 17 additions & 14 deletions docs/capabilities.md
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Expand Up @@ -291,20 +291,23 @@ skips have hardware-independent test coverage.

## Cortex-M target operations

| Capability | Implemented | Validation and boundary |
| ------------------------------------- | ----------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ |
| CPUID read and decode | Yes | Accepts any aligned-word reader and validates a plausible Arm Cortex-M identity. |
| Physical identity read | HIL | Opt-in FTDI/SWD/DAP/MEM-AP integration test. |
| Cortex-M0 acquisition and halt/resume | HIL | Two CMSIS-DAP micro:bit sessions at a requested 1 MHz stopped a CPU counter during halt and observed progress after resume and release. Both restored initially disabled debug and running state before Arm debug owner close. Earlier sessions preserved initially enabled debug. Cleanup failures remain covered only by behavioral tests; see the [control evidence](cortexm.md#hardware-evidence). |
| Cortex-M0 step | HIL | `Target.Step` requires an owned halt and returns halted. Two fresh micro:bit sessions checked PC/R0/RAM across 13 steps each, resume, and release with disabled debug restored. Competing events and failure cleanup have behavioral coverage; see the [step bench](cortexm.md#step-bench). |
| Register reads | Yes | Halted Cortex-M0 R0–R12, SP, LR, PC, XPSR, MSP, and PSP through `ReadRegister`. Two fresh CMSIS-DAP micro:bit sessions read all 19 registers; transfer failures and cleanup have behavioral coverage. |
| Register writes | Yes | Halted Cortex-M0 writes except XPSR; aligned SP/MSP/PSP and even PC values. Writes persist after release. Behavioral tests cover staging, uncertain selection, and pending cleanup. Two micro:bit sessions wrote and restored R4, SP, MSP, PSP, and PC before resuming; see the [register bench](cortexm.md#register-bench). |
| Reset | No | No architectural or pin-reset operation exists. |
| Breakpoints or watchpoints | No | No target instrumentation API exists. |
| Firmware or runtime loading | No | No ELF loader, image-placement policy, or flash driver exists. |

Identity covers Cortex-M; acquired control currently accepts Cortex-M0 only. See
[Cortex-M control](cortexm.md) for its effects and cleanup limits.
| Capability | Implemented | Validation and boundary |
| -------------------------------------- | ----------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ |
| CPUID read and decode | Yes | Accepts any aligned-word reader and validates a plausible Arm Cortex-M identity. |
| Physical identity read | HIL | Opt-in FTDI/SWD/DAP/MEM-AP integration test. |
| Cortex-M0 acquisition and halt/resume | HIL | Two CMSIS-DAP micro:bit sessions at a requested 1 MHz stopped a CPU counter during halt and observed progress after resume and release. Both restored initially disabled debug and running state before Arm debug owner close. Earlier sessions preserved initially enabled debug. Cleanup failures remain covered only by behavioral tests; see the [control evidence](cortexm.md#hardware-evidence). |
| Cortex-M33 acquisition and halt/resume | HIL | Two RP2350 core-0/J-Link sessions at 1 MHz stopped a RAM counter during halt, observed counter progress after resume and release, and restored disabled debug. Secure invasive debug permission is required; register access and stepping remain M0-only. |
| Cortex-M0 step | HIL | `Target.Step` requires an owned halt and returns halted. Two fresh micro:bit sessions checked PC/R0/RAM across 13 steps each, resume, and release with disabled debug restored. Competing events and failure cleanup have behavioral coverage; see the [step bench](cortexm.md#step-bench). |
| Register reads | Yes | Halted Cortex-M0 R0–R12, SP, LR, PC, XPSR, MSP, and PSP through `ReadRegister`. Two fresh CMSIS-DAP micro:bit sessions read all 19 registers; transfer failures and cleanup have behavioral coverage. |
| Register writes | Yes | Halted Cortex-M0 writes except XPSR; aligned SP/MSP/PSP and even PC values. Writes persist after release. Behavioral tests cover staging, uncertain selection, and pending cleanup. Two micro:bit sessions wrote and restored R4, SP, MSP, PSP, and PC before resuming; see the [register bench](cortexm.md#register-bench). |
| Reset | No | No architectural or pin-reset operation exists. |
| Breakpoints or watchpoints | No | No target instrumentation API exists. |
| Firmware or runtime loading | No | No ELF loader, image-placement policy, or flash driver exists. |

Identity covers Cortex-M; acquired halt/resume control accepts Cortex-M0 and
Cortex-M33. M33 requires Secure invasive debug permission and excludes register
access and stepping. See [Cortex-M control](cortexm.md) for its effects and
cleanup limits.

## Executable surfaces

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