Support halted Cortex-M33 register access.

[jon]

Allow ReadRegister and WriteRegister on an acquired, halted Cortex-M33 using the same register set as Cortex-M0. SP selects the current stack; MSP and PSP select the main and process stacks in the halted security state. Register access does not change security state or DSCSR bank selection. XPSR remains read-only, and M33 stepping remains unsupported.

Previously, this read rejected an acquired M33 before memory traffic:

pc, err := core.ReadRegister(ctx, cortexm.PC)

It now reads the halted processor's debug return address. A complete use through a borrowed core-0 MEM-AP selected with dap.APAt(0x2000) is:

core, err := cortexm.Acquire(ctx, memory)
if err == nil {
    err = core.Halt(ctx)
}
if err == nil {
    var pc uint32
    pc, err = core.ReadRegister(ctx, cortexm.PC)
    if err == nil {
        fmt.Printf("PC=%#x\n", pc)
    }
}
if err == nil {
    err = core.WriteRegister(ctx, cortexm.R4, 42)
}
if err == nil {
    err = core.Resume(ctx)
}
cleanupErr := core.Release(cleanupCtx)
err = errors.Join(err, cleanupErr)
// Release the memory owner only if cleanupErr is nil.
// Otherwise retain core and its memory owner for another release attempt.

The caller supplies ctx and a live cleanupCtx, including after operation cancellation. R4 remains changed after release. An inherited halt allows register access but grants no permission to resume it.

Why

M33 control was available, but register access still rejected the architecture. The existing DCRSR selectors cover its common register set without changing security state. Register-status reads now apply M33 permission and snap-stall checks and observe sticky restart status. A restart during a pending transfer prevents automatic cleanup even if the processor has already halted again; the new halt cannot establish that the original transfer completed.

Hardware evidence

On Nostalgia, two fresh sessions used J-Link EDU Mini V2 000802011345, 1 MHz SWD, and RP2350 core 0 at AP 0x2000, CPUID 0x411fd210. The already-running RAM counter was exercised with:

OSTIOLE_RP2350_HIL_CONTROL=1 \
OSTIOLE_RP2350_HIL_REGISTERS=1 \
OSTIOLE_RP2350_HIL_PROGRAM=c20737e61153b272322548e8e6db5c420f0c148d6707ca4412c309f70415065a \
go test -tags integration ./target/cortexm -run '^TestHILRP2350Registers$' -count=1 -v

Both sessions read all 19 registers and wrote and restored R4, SP, MSP, PSP, and PC. The full snapshot matched before resume; DSCSR stayed 0x00030000. The counter stopped while halted and advanced after resume and release. Initially disabled debug and running state were restored before Arm owner close; both owners closed successfully.

This covers Secure state on core 0. Non-secure stack selection and transfer failure paths have behavioral coverage. Temporary stack and PC values were not executed. No security-state switch or core-1 control was performed, and state after Arm owner close was not measured. Flash was untouched; the existing RAM program remains running.

Documentation

Update the register API, Cortex-M guide, architecture and composition guides, capability table, and README for M33 register access and its current-state stack semantics. The guide includes the gated hardware procedure and observations, and clarifies that inherited cross-trigger routing can couple cores.

[jon]

@codex review

[chatgpt-codex-connector]

Codex Review Summary

This comment shows the latest Codex review activity on this pull request.

Review	Status	Commit	Review trigger
📝 Code Review	✅ Completed 2026-09-28T05:54:37.739993Z	9f13f29	Manual request
🔒 Security Review	✅ Completed 2026-09-28T05:55:06.117042Z	9f13f29	PR opened

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[chatgpt-codex-connector]

Codex Review: Didn't find any major issues. 👍

Reviewed commit: 9f13f29acf

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