Issues

• QDSUB clamps an in-range final result because the intermediate doubling set Q

  krevanth/ZAP#14 · Filter by author canxin121 opened on Nov 2, 2026
  3

• Conditional SMULLS re-evaluates its predicate after writing low-word flags

  krevanth/ZAP#13 · Filter by author canxin121 opened on Nov 2, 2026

• SMULTT adds R0 even though the instruction has no accumulator

  krevanth/ZAP#12 · Filter by author canxin121 opened on Nov 2, 2026

• SMLATB sign-extends the upper halfword from bit 16 instead of bit 31

  krevanth/ZAP#11 · Filter by author canxin121 opened on Nov 2, 2026

• SMLALBT right-shifts the accumulated result by 16

  krevanth/ZAP#10 · Filter by author canxin121 opened on Nov 2, 2026

• SMLAWT falls through to full-word multiplication

  krevanth/ZAP#9 · Filter by author canxin121 opened on Nov 2, 2026

• QADD doubles one input as if it were QDADD

  krevanth/ZAP#8 · Filter by author canxin121 opened on Nov 2, 2026

• Saturating arithmetic overwrites NZCV

  krevanth/ZAP#7 · Filter by author canxin121 opened on Nov 2, 2026

• Register-offset LDRD expands the offset and second destination incorrectly

  krevanth/ZAP#6 · Filter by author canxin121 opened on Nov 2, 2026

• Post-indexed STRD computes an incorrect second store address

  krevanth/ZAP#5 · Filter by author canxin121 opened on Nov 2, 2026

• Few questions Revanth.

  krevanth/ZAP#4 · Filter by author srvedulageth opened on Jun 23, 2026
  7

• zap_wb_merger,sv: ACK for I-Cache access is also taken as ACK for D-Cache access

  krevanth/ZAP#3 · Filter by author srvedulageth opened on Jun 4, 2026
  10

• When Cache and MMU enabled, code is getting corrupted

  krevanth/ZAP#2 · Filter by author srvedulageth opened on Apr 26, 2026
  2

  

• Why no Dockerfile

  krevanth/ZAP#1 · Filter by author ErezBinyamin opened on Jan 12, 2025