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273 workflow runs
273 workflow runs

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Model finite ESP32-S3 RMT TX loops and driver batching ci #273: Commit a797cae pushed by levkropp
9m 12s master
master
9m 12s
ci: retry transient ESP32 core download failures ci #272: Commit 039ba59 pushed by levkropp
13m 15s master
master
13m 15s
ci: pin checksum-verified Arduino CLI download ci #271: Commit abee71c pushed by levkropp
4m 32s master
master
4m 32s
feat(s3): model data-only RMT carrier pad waveform ci #270: Commit 5c4f1f9 pushed by levkropp
4m 7s master
master
4m 7s
feat(s3): sample unwatched RMT TX on GPIO input reads ci #269: Commit 5153590 pushed by levkropp
8m 6s master
master
8m 6s
test(s3): gate native ESP-IDF RMT TX/RX GPIO loopback ci #268: Commit d0289b9 pushed by levkropp
11m 36s master
master
11m 36s
Route observed S3 RMT TX edges through GPIO matrix ci #267: Commit 6bbe0ed pushed by levkropp
11m 8s master
master
11m 8s
Fix strict CI build for S3 RMT input routing ci #266: Commit 567726a pushed by levkropp
11m 23s master
master
11m 23s
Route S3 GPIO matrix edges into RMT RX ci #265: Commit 1e956ff pushed by levkropp
4m 59s master
master
4m 59s
Model S3 GPIO input buffers and driven pad feedback ci #264: Commit c7099e2 pushed by levkropp
10m 3s master
master
10m 3s
Gate stock ESP-IDF S3 I2C master transactions ci #263: Commit 3af4b79 pushed by levkropp
11m 9s master
master
11m 9s
Model ESP32-S3 GPIO open-drain drive state ci #262: Commit b15c587 pushed by levkropp
11m 2s master
master
11m 2s
Gate S3 ESP-IDF GPIO ISR delivery from host pin edges ci #261: Commit d18c21b pushed by levkropp
11m 1s master
master
11m 1s
Model S3 USB PHY routing and replay ESP-IDF driver RX/TX ci #260: Commit 2eaec98 pushed by levkropp
9m 14s master
master
9m 14s
Honor ESP32-S3 USB Serial JTAG clock and reset ci #259: Commit f440089 pushed by levkropp
10m 52s master
master
10m 52s
Model ESP32-S3 UART peripheral clock and reset gates ci #258: Commit 117179a pushed by levkropp
8m 6s master
master
8m 6s
Model ESP32-S3 RTC power-sequencer registers and stall enable ci #257: Commit bdfedb0 pushed by levkropp
7m 36s master
master
7m 36s
Model optional ESP32-S3 octal PSRAM with cache-backed Arduino gate ci #256: Commit 7edee6d pushed by levkropp
7m 23s master
master
7m 23s
Add verified GD25Q64C SFDP profile for 8 MiB S3 flash ci #255: Commit ba55698 pushed by levkropp
10m 20s master
master
10m 20s
Model no-slave SPI-memory transactions before decoding opcodes ci #254: Commit a447d98 pushed by levkropp
10m 34s master
master
10m 34s
Route ESP32-S3 GDMA channel interrupts to both cores ci #253: Commit 8d7d37b pushed by levkropp
10m 8s master
master
10m 8s
Honor GD25Q32C block protection for NOR writes ci #252: Commit db791f8 pushed by levkropp
10m 43s master
master
10m 43s
Retain external NOR state across SoC reset and profile deep-sleep pow… ci #251: Commit 9127dff pushed by levkropp
8m 48s master
master
8m 48s
Model GD25Q32C SFDP and preserve NOR status across flash reset ci #250: Commit 7c5cc1c pushed by levkropp
10m 47s master
master
10m 47s
Discover S3 lwIP socket ranges from guest VFS registration ci #249: Commit 4c93c5d pushed by levkropp
10m 46s master
master
10m 46s