fix(stm32wl): enable GPS on Wio-E5 via LPUART1 and HSI16 clock routing with graceful fallback - #11740
fix(stm32wl): enable GPS on Wio-E5 via LPUART1 and HSI16 clock routing with graceful fallback#11740t-miura wants to merge 4 commits into
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- update LPUART1 clock configuration for GNSS/GPS support with LPUART - update wio-e5 variant to use LPUART1(PC1/PC0), also enabling LSE and RTC
…-clock-wio-e5-gps
…ue-with-no-gps on failure fix(stm32wl): gracefully disable GPS if LPUART1 is selected but not usable
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Included review availability: Your plan provides up to 8 included reviews per hour; 7 remain after this review. 📝 WalkthroughWalkthroughChangesThe Wio-E5 variant moves GPS to LPUART1. STM32WL startup configures the LPUART1 clock through HSI16. GPS probing and creation stop when serial initialization or LPUART1 availability checks fail. STM32WL GPS support
Estimated code review effort: 3 (Moderate) | ~20 minutes Merge Risk: ⚪ Minimal · up to Wio-E5 GPS now uses LPUART1 with validated clock and serial initialization, disabling GPS safely if setup fails. No current merge-blocking risk is identified. Sequence Diagram(s)sequenceDiagram
participant WioE5
participant stm32wlSetup
participant stm32wlLpuartSetup
participant createGps
participant SerialLP1
WioE5->>stm32wlSetup: start platform setup
stm32wlSetup->>stm32wlLpuartSetup: configure LPUART1 clock
stm32wlLpuartSetup-->>stm32wlSetup: report clock availability
WioE5->>createGps: initialize GPS
createGps->>SerialLP1: begin GPS baud rate
SerialLP1-->>createGps: report initialization status
createGps->>WioE5: create GPS or disable GPS
Suggested reviewers: 🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
Full details: Docstring CoverageExplanation Docstring coverage is 30.00% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 10 functions across 4 files. (1 skipped: 1 unsupported.)
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Inline comments:
In `@src/gps/GPS.cpp`:
- Around line 2068-2071: Update createGps so STM32 serial initialization via
_serial_gps and begin(GPS_BAUDRATE) occurs before new_gps->up() and other GPS
side effects, or explicitly undo all setup before returning nullptr on failure;
preserve the existing warning and failed-creation behavior.
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src/gps/GPS.cppsrc/platform/stm32wl/architecture.hsrc/platform/stm32wl/main-stm32wl.cppvariants/stm32/wio-e5/platformio.inivariants/stm32/wio-e5/variant.h
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reverting to draft as upstream now has fix for Serial()'s lockup: stm32duino/Arduino_Core_STM32#3074 while new approach may have changes to GPS.cpp in wider blast radius, so I'll take some time to examine the situation across all available platforms. |
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Summary
Enables reliable GNSS/GPS support on Seeed Wio-E5 (STM32WLE5JC) and resolves core STM32 serial lockup traps by:
PA2/PA3(USART2) toPC1/PC0(LPUART1) to permanently eliminate ST ROM bootloader DFU lockups (ST AN2606).3 * baud <= f_CK <= 4096 * baud), supporting both 9600 boot baud (which overflows 20-bit BRR on default 48 MHz PCLK1, as well as 4800 baud) and 115200 fast probing (which underflows on 32.768 kHz LSE).HAS_LSEvia a dedicatedstm32wlLpuartSetup()helper so that boards without a 32.768 kHz crystal still configure LPUART1 correctly when enabled.createGps() → nullptr, keeping the node in mesh mode ("Run without GPS").createGps(),verifyCachedProbePresence(), andprobe()) by validating port readiness viaif (!*_serial_gps)after everybegin()call onARCH_STM32(and prior to GPS hardware side-effects increateGps()).variants/stm32/wio-e5/platformio.iniforMESHTASTIC_EXCLUDE_SERIAL=1.Note: While this is targeted against Wio-E5(LoRa-E5)'s issue, but will also prevents other
stm32wlvariants from same issue when LPUART is being used for GPS' seral(currently none exists, but may happen on custom builds and such).Root Cause & Technical Details
1. LPUART1 Dual Clock Constraints & Upstream Core Deadlock (stm32duino/Arduino_Core_STM32#3071)
Per the STMicroelectronics STM32WL Reference Manual (RM0461, Section 29.4.4 LPUART baud rate generation):
Because
BRRis a 20-bit register (BRR <= 0xFFFFF) and requiresBRR >= 0x300for sampling, the peripheral kernel clockf_CKmust strictly satisfy the dual bounds:This creates a mutual exclusion trap between the default clock sources:
LSE (32.768 kHz) – Lower Bound Failure (
f_CK < 3 * baud):Higher GNSS baud rates (38400, 115200) are physically impossible with LSE.
PCLK1 (48 MHz, default when LSE is absent/disabled) – Upper Bound Failure (
f_CK > 4096 * baud):In STM32Duino on Wio-E5, MSI boots at 48 MHz and APB1 prescaler is DIV1, so default reset PCLK1 is 48 MHz. The 20-bit BRR register overflows (
BRR > 0xFFFFF):The standard GPS boot baud rate (9600 baud) is physically impossible on 48 MHz PCLK1, which is critical.
Furthermore, current probing goes low as 4800 baud, and this is also impossible on PCLK1 as well.
The Solution: HSI16 (16 MHz):
At 16 MHz, the valid span is
3906 baud <= baud <= 5.33 Mbaud, allowing seamless operation across all GNSS baud rates from 4800 baud to 115200 baud.In STM32duino, baud rates outside the
[3 * baud, 4096 * baud]range failuart_init()and leave_ready = false. BecauseUart::write()does not check_ready, it loops indefinitely inwhile (!availableForWrite())once the TX buffer fills (interrupts are never enabled on an unready port).2. DFU Lockup on PA2/PA3 (ST AN2606)
PA2/PA3(USART2). Per ST Application Note AN2606 (STM32 microcontroller system memory boot mode), the STM32WL internal ROM bootloader monitors USART1 (PB6/PB7) and USART2 (PA2/PA3) with autobaud detection at startup.PA2/PA3and actively transmits NMEA sentences during boot or a DFU reboot, the ROM bootloader captures the serial stream, locks onto a spurious baud rate, and wedges DFU flashing sessions.PC0(RX) andPC1(TX) on LPUART1 (AF8).Solution & Architecture
1. Bounded HSI16 Clock Bringup & LSE Decoupling
In
main-stm32wl.cpp:stm32wlLpuartSetup(), called fromstm32wlSetup()regardless ofHAS_LSE.__HAL_RCC_HSI_ENABLE()) and pollsRCC_FLAG_HSIRDYwith a 1000ms timeout (STM32WL_LPUART1_SWITCH_TIMEOUT_MS) usingThrottle::isWithinTimespanMs()withdelay(1)yields to service the watchdog.RCC->CCIPRregister readback.__HAL_RCC_HSI_DISABLE()) to eliminate ~150–200 µA quiescent leakage, and leavesstm32wlLpuartValid = false.2. Graceful Degradation in Factory Creation
In
GPS::createGps():_serial_gps == &SerialLP1 && !stm32wlLpuartAvailable(), creation immediately aborts and returnsnullptrbefore allocating heap memory, configuring GPIOs, or touching the UART port.main.cpptakes its"Run without GPS"fallback branch, keeping the node fully functional on the mesh as a LoRa router.3. Comprehensive Driver Readiness Contract
This mitigates the issue on STM32duino: stm32duino/Arduino_Core_STM32#3071
In
src/gps/GPS.cpp, addedif (!*_serial_gps)checks (HardwareSerial::operator bool()) after everybegin()call onARCH_STM32:createGps()): Configures and validates serial port readiness before allocatingnew GPS()or initiating hardware side effects (up(), reset/power pins), guaranteeing zero heap leaks or stranded active peripherals if initialization fails.verifyCachedProbePresence()): Clears the probe cache and returnsfalseifbegin(cachedProbeBaud)fails.probe()): Skips_serial_gps->write(...)and returnsGNSS_MODEL_UNKNOWNifbegin(serialSpeed)fails, advancing safely to the next baud rate without deadlocking.Target Isolation & Scope
#if defined(ARCH_STM32WL) && defined(ENABLE_HWSERIALLP1).rak3172):ENABLE_HWSERIALLP1is not set; they incur zero code or runtime overhead._serial_gps == &SerialLP1check guarantees that if LPUART1 is enabled for another peripheral on a board, GPS configured on a different UART (e.g.Serial1) is not blocked.Verification
wio-e5(SUCCESS, Flash: 94.3%, RAM: 40.5%). Tested on actual hardware as well(Wio-E5 mini)rak3172(SUCCESS, Flash: 88.1%, RAM: 39.8%) to verify zero regressions on other STM32WL targets.While it is difficult to physically break/disable the HSI16 as it's on silicon,
it is still possible to simulate "faulty HSI16", by commenting out whole code block in
main-stm32wl.cpp,I ran some tests below, and verified these code does actually prevents LPUART1 to be used when it should not be.
Test 1: No LSE&RTC, but with this PR applied, GPS on same pin(LPUART1, PC0/1)
Test 2: LSE&RTC Enabled, and failed to switch LPUART kernel clock to HSI16(simulated fault)
Test 3: LSE&RTC Disabled, also failed to switch LPUART kernel clock to HSI16
Test 4: GPS Probing with various baud rate with this PR applied, LSE&RTC enabled, GPS not connected
Expected Behavior: Probing through all baud rate from 4800 to 115200, and reverts to 9600 baud as GPS is not connected
Result: PASSED
Test 5: Normal Situation(LSE/RTC Enabled, U-blox NEO-7M connected)
Expected Behavior: Detects connected GPS module, update the module config, sets time from NMEA, and tries to lock.
Result: PASSED (also got a valid position fix some minutes later as well)
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Summary by CodeRabbit
New Features
Bug Fixes