[Nexthop][feature] "asic_config_v3" - Support multiple management ports

docs/docs/developing/asic_config_v3/schema_field_reference.md

@@ -54,8 +54,8 @@ following fields.
 | `port_config` | XGS. Front-panel port settings: `default_speed` (in Mbps), `speed_to_fec` (mapping from speed to FEC mode), `enable` (the value emitted for `PC_PORT.ENABLE`), and `pc_port_overrides` (extra `PC_PORT` key/value lines emitted verbatim, for example `LINK_TRAINING`). This object is distinct from the DNX `port_config` string inside `asic_config_params`. |
 | `cpu_port` | XGS. CPU port settings: `speed` (in Mbps) and `num_lanes`. |
 | `mgmt_port` | XGS. Management port settings: `enabled` (whether the port is emitted at all), `enable` (the `PC_PORT.ENABLE` value), `in_port_block` (include the port in the `PORT` MTU range), and `speed_variants` (per-speed settings keyed by speed). |
-| `mgmt_port_overrides` | XGS. Platform overrides of the ASIC-level management port defaults: `logical_id`, `physical_id`, `speed`, `num_lanes`, and `fec`. |
-| `port_mapping_overrides` | XGS. Adjustments to the logical-to-physical port mapping formula: `core_range` (which cores participate, for example `"0-15,48-63"`), `num_lp_ports_on_even_core`, `num_logical_ports_per_datapath`, `lp_start_step_offset`, `lp_offset_simple`, `special_core_offset_apply_all`, and `exclude_logical_ports` (logical port IDs omitted from `PC_PORT_PHYS_MAP`, `PC_PORT`, and `PORT`, for front-panel ports that are not populated on the platform). |
+| `mgmt_port_overrides` | XGS. List of platform overrides of the ASIC-level management port defaults (`logical_id`, `physical_id`, `speed`, `num_lanes`, and `fec`), overriding the port at the same index. Entries beyond the defaults list declare additional ports and must be complete. Duplicate logical or physical port identifiers are rejected. |
+| `port_mapping_overrides` | XGS. Adjustments to the logical-to-physical port mapping formula: `core_range` (which cores participate, for example `"0-15,48-63"`), `num_lp_ports_on_even_core`, `num_logical_ports_per_datapath`, `lp_start_step_offset`, `lp_offset_simple`, and `exclude_logical_ports` (logical port IDs omitted from `PC_PORT_PHYS_MAP`, `PC_PORT`, and `PORT`, for front-panel ports that are not populated on the platform). |
 | `platform_sai_overrides` | XGS. Platform-level SAI settings. These take precedence within the layered `global` sources and override the ASIC-level SAI overrides. |
 | `platform_sdk_overrides` | DNX. Platform-level SOC properties applied on top of the ASIC `base_sdk_settings` and declarative tables. Keys carry their SOC suffix inline. |
 | `device_config_overrides` | XGS. Key/value pairs written to the `DEVICE_CONFIG` output table, for example clock frequencies. |
@@ -101,7 +101,7 @@ files under `fboss/configs/asic_vendors/broadcom/xgs/asics/`.
 | `port_architecture` | Core, lane, and datapath layout consumed by the port mapping logic: `num_cores`, `num_lanes_per_core`, `num_logical_ports_per_datapath`, `num_physical_ports_per_datapath`, and `num_lp_ports_on_even_core_default`. |
 | `mmu_size` | MMU buffer size in bytes. Also used as the `MAX_FRAME_SIZE` and port MTU values. |
 | `table_names` | Ordered list of output YAML table names. Controls which tables appear in the output and their order. |
-| `mgmt_port_defaults` | Default management port settings: `logical_id`, `physical_id`, `speed`, `num_lanes`, and `fec`. Platforms may override these per variant. |
+| `mgmt_port_defaults` | List of default management port settings, one entry per port: `logical_id`, `physical_id`, `speed`, `num_lanes`, and `fec`. Platforms may override these per variant. |
 | `preamble_support` | Whether the ASIC supports a preamble section prepended to the output YAML. When `false`, any `preamble_file` declared by a platform is ignored. |
 | `global_defaults` | ASIC-specific SDK settings copied into the `global` output table. |
 | `sai_overrides` | ASIC-specific SAI settings layered on top of the vendor SAI common values. |

fboss/configs/asic_vendors/broadcom/xgs/asics/tomahawk5.json

@@ -26,13 +26,15 @@
     "PC_PMD_FIRMWARE",
     "DLB_ECMP_CONFIG"
   ],
-  "mgmt_port_defaults": {
-    "logical_id": 76,
-    "physical_id": 513,
-    "speed": 100000,
-    "num_lanes": 4,
-    "fec": "PC_FEC_RS528"
-  },
+  "mgmt_port_defaults": [
+    {
+      "logical_id": 76,
+      "physical_id": 513,
+      "speed": 100000,
+      "num_lanes": 4,
+      "fec": "PC_FEC_RS528"
+    }
+  ],
   "preamble_support": true,
 
   "global_defaults": {

fboss/configs/asic_vendors/broadcom/xgs/asics/tomahawk6.json

@@ -26,13 +26,15 @@
     "DLB_ECMP_CONFIG",
     "PHB_CONTROL"
   ],
-  "mgmt_port_defaults": {
-    "logical_id": 76,
-    "physical_id": 513,
-    "speed": 100000,
-    "num_lanes": 4,
-    "fec": "PC_FEC_RS528"
-  },
+  "mgmt_port_defaults": [
+    {
+      "logical_id": 76,
+      "physical_id": 513,
+      "speed": 100000,
+      "num_lanes": 4,
+      "fec": "PC_FEC_RS528"
+    }
+  ],
   "preamble_support": false,
 
   "global_defaults": {

fboss/configs/platforms/arista/icecube800banw/asic_config/asic_config.json

@@ -28,10 +28,12 @@
       "enabled": true,
       "enable": 1
     },
-    "mgmt_port_overrides": {
-      "logical_id": 268,
-      "physical_id": 514
-    },
+    "mgmt_port_overrides": [
+      {
+        "logical_id": 268,
+        "physical_id": 514
+      }
+    ],
     "port_mapping_overrides": {
       "num_logical_ports_per_datapath": 16,
       "lp_start_step_offset": 2,

fboss/configs/platforms/celestica/icecube800bc/asic_config/asic_config.json

@@ -34,10 +34,12 @@
         }
       }
     },
-    "mgmt_port_overrides": {
-      "logical_id": 268,
-      "physical_id": 514
-    },
+    "mgmt_port_overrides": [
+      {
+        "logical_id": 268,
+        "physical_id": 514
+      }
+    ],
     "port_mapping_overrides": {
       "num_logical_ports_per_datapath": 18,
       "lp_start_step_offset": 0,

fboss/configs/platforms/celestica/icetea800bc/asic_config/asic_config.json

@@ -28,10 +28,12 @@
       "enabled": true,
       "enable": 1
     },
-    "mgmt_port_overrides": {
-      "logical_id": 268,
-      "physical_id": 514
-    },
+    "mgmt_port_overrides": [
+      {
+        "logical_id": 268,
+        "physical_id": 514
+      }
+    ],
     "port_mapping_overrides": {
       "num_logical_ports_per_datapath": 16,
       "lp_start_step_offset": 2,

fboss/configs/platforms/celestica/ladakh800bcls/asic_config/asic_config.json

@@ -30,10 +30,12 @@
       "enabled": true,
       "in_port_block": true
     },
-    "mgmt_port_overrides": {
-      "logical_id": 268,
-      "physical_id": 514
-    },
+    "mgmt_port_overrides": [
+      {
+        "logical_id": 268,
+        "physical_id": 514
+      }
+    ],
     "port_mapping_overrides": {
       "num_logical_ports_per_datapath": 18,
       "lp_start_step_offset": 0,

fboss/configs/platforms/celestica/tahansb800bc/asic_config/asic_config.json

@@ -26,10 +26,12 @@
     "mgmt_port": {
       "enabled": true
     },
-    "mgmt_port_overrides": {
-      "logical_id": 268,
-      "physical_id": 514
-    },
+    "mgmt_port_overrides": [
+      {
+        "logical_id": 268,
+        "physical_id": 514
+      }
+    ],
     "port_mapping_overrides": {
       "num_logical_ports_per_datapath": 18,
       "lp_start_step_offset": 0,

fboss/lib/asic_config_v3/generators/broadcom_xgs_generator.py

@@ -5,6 +5,7 @@
 from typing import Any
 
 import yaml
+
 from fboss.lib.asic_config_v3.base_generator import BaseAsicConfigGenerator
 from fboss.lib.asic_config_v3.paths import AsicConfigPaths
 from fboss.lib.platform_mapping_v2.platform_mapping_v2 import PlatformMappingParser
@@ -52,10 +53,14 @@ def __init__(
         self.num_ports_per_core: int = self.platform_config.get("num_ports_per_core", 2)
         self.mmu_size: int = self.asic_config.get("mmu_size", 9416)
 
-        # Compute lanes_per_port from ASIC port_architecture and platform num_ports_per_core
+        # lanes_per_port is derived from the ASIC port architecture unless the
+        # platform wires only a subset of chip lanes per port and overrides it
+        # explicitly via num_lanes_per_port.
         port_arch = self.asic_config.get("port_architecture", {})
         num_lanes_per_core = port_arch.get("num_lanes_per_core", 8)
-        self.lanes_per_port: int = num_lanes_per_core // self.num_ports_per_core
+        self.lanes_per_port: int = self.platform_config.get(
+            "num_lanes_per_port", num_lanes_per_core // self.num_ports_per_core
+        )
 
     @property
     def output_extension(self) -> str:
@@ -280,6 +285,49 @@ def _get_logical_port_to_physical_port_mapping(self) -> list[list[int]]:
 
         return logical_to_physical_port_mapping
 
+    def _get_mgmt_ports(self) -> list[dict[str, Any]]:
+        """Return one merged settings dict per management port.
+
+        ``mgmt_port_defaults`` and ``mgmt_port_overrides`` are lists with one
+        entry per port; overrides merge onto the defaults entry at the same
+        index. Entries beyond the defaults list must be complete, and ports
+        must not share logical or physical identifiers.
+        """
+        defaults = self.asic_config.get("mgmt_port_defaults", [])
+        overrides = self.variant_config.get("mgmt_port_overrides", [])
+
+        ports = []
+        for i in range(max(len(defaults), len(overrides))):
+            port = {
+                **(defaults[i] if i < len(defaults) else {}),
+                **(overrides[i] if i < len(overrides) else {}),
+            }
+            if i >= len(defaults):
+                missing = {
+                    "logical_id",
+                    "physical_id",
+                    "speed",
+                    "num_lanes",
+                    "fec",
+                } - port.keys()
+                if missing:
+                    raise ValueError(
+                        f"mgmt_port_overrides entry {i} declares an additional "
+                        "management port with no mgmt_port_defaults entry to "
+                        f"inherit from, so it must be complete; missing "
+                        f"{sorted(missing)}"
+                    )
+            ports.append(port)
+
+        for field in ("logical_id", "physical_id"):
+            ids = [port[field] for port in ports if field in port]
+            duplicates = sorted({v for v in ids if ids.count(v) > 1})
+            if duplicates:
+                raise ValueError(
+                    f"Management ports declare duplicate {field} values: {duplicates}"
+                )
+        return ports
+
     def _generate_logical_port_to_physical_port_mapping(
         self, mgmt_port: bool = False
     ) -> None:
@@ -294,18 +342,12 @@ def _generate_logical_port_to_physical_port_mapping(
             pm_value = (f"PC_PHYS_PORT_ID: {lp_map[1]}",)
             self.values["PC_PORT_PHYS_MAP"][pm_key] = pm_value
 
-        if mgmt_port:
-            mgmt_defaults = self.asic_config.get("mgmt_port_defaults", {})
-            mgmt_overrides = self.variant_config.get("mgmt_port_overrides", {})
-            logical_id = mgmt_overrides.get(
-                "logical_id", mgmt_defaults.get("logical_id", 76)
-            )
-            physical_id = mgmt_overrides.get(
-                "physical_id", mgmt_defaults.get("physical_id", 513)
-            )
-            pm_key = (f"PORT_ID: {logical_id}",)
-            pm_value = (f"PC_PHYS_PORT_ID: {physical_id}",)
-            self.values["PC_PORT_PHYS_MAP"][pm_key] = pm_value
+        mgmt_port_config = self.variant_config.get("mgmt_port", {})
+        if mgmt_port and mgmt_port_config.get("enabled", False):
+            for port in self._get_mgmt_ports():
+                pm_key = (f"PORT_ID: {port['logical_id']}",)
+                pm_value = (f"PC_PHYS_PORT_ID: {port['physical_id']}",)
+                self.values["PC_PORT_PHYS_MAP"][pm_key] = pm_value
 
     def _generate_lane_map(self) -> None:
         """Generate lane map entries in PC_PM_CORE."""
@@ -346,8 +388,6 @@ def _generate_port_config(self, mgmt_port: bool = False) -> None:
         port_config = self.variant_config.get("port_config", {})
         cpu_port_config = self.variant_config.get("cpu_port", {})
         mgmt_port_config = self.variant_config.get("mgmt_port", {})
-        mgmt_defaults = self.asic_config.get("mgmt_port_defaults", {})
-        mgmt_overrides = self.variant_config.get("mgmt_port_overrides", {})
 
         default_speed = port_config.get("default_speed", 400000)
         speed_to_fec = port_config.get("speed_to_fec", {})
@@ -383,31 +423,25 @@ def _generate_port_config(self, mgmt_port: bool = False) -> None:
         self.values["PC_PORT"][pc_key] = pc_value
 
         if mgmt_port and mgmt_port_config.get("enabled", False):
-            logical_id = mgmt_overrides.get(
-                "logical_id", mgmt_defaults.get("logical_id", 76)
-            )
-            mgmt_speed = mgmt_overrides.get("speed", mgmt_defaults.get("speed", 100000))
-            mgmt_num_lanes = mgmt_overrides.get(
-                "num_lanes", mgmt_defaults.get("num_lanes", 4)
-            )
-            mgmt_fec = mgmt_overrides.get(
-                "fec", mgmt_defaults.get("fec", "PC_FEC_RS528")
-            )
             mgmt_enable = mgmt_port_config.get("enable", 0)
+            for port in self._get_mgmt_ports():
+                logical_id = port["logical_id"]
+                mgmt_port_key = (f"PORT_ID: {logical_id}",)
+                mgmt_port_value = (
+                    f"ENABLE: {mgmt_enable}",
+                    f"SPEED: {port['speed']}",
+                    f"NUM_LANES: {port['num_lanes']}",
+                    f"FEC_MODE: {port['fec']}",
+                    f"MAX_FRAME_SIZE: {self.mmu_size}",
+                )
+                self.values["PC_PORT"][mgmt_port_key] = mgmt_port_value
 
-            mgmt_port_key = (f"PORT_ID: {logical_id}",)
-            mgmt_port_value = (
-                f"ENABLE: {mgmt_enable}",
-                f"SPEED: {mgmt_speed}",
-                f"NUM_LANES: {mgmt_num_lanes}",
-                f"FEC_MODE: {mgmt_fec}",
-                f"MAX_FRAME_SIZE: {self.mmu_size}",
-            )
-            self.values["PC_PORT"][mgmt_port_key] = mgmt_port_value
+                # Optionally include the mgmt ports in the PORT (MTU) range
+                # alongside FP.
+                if mgmt_port_config.get("in_port_block", False):
+                    port_ranges.append(f"[{logical_id}, {logical_id}]")
 
-            # Optionally include the mgmt port in the PORT (MTU) range alongside FP.
             if mgmt_port_config.get("in_port_block", False):
-                port_ranges.append(f"[{logical_id}, {logical_id}]")
                 port_ranges_str = ", ".join(port_ranges)
                 pc_key = (f"PORT_ID: [{port_ranges_str}]",)
 

fboss/lib/asic_config_v3/schemas/broadcom_xgs_asic_config.schema.json

@@ -81,31 +81,11 @@
             "minItems": 1
         },
         "mgmt_port_defaults": {
-            "type": "object",
-            "description": "Default settings for the management (out-of-band) port.",
-            "required": ["logical_id", "physical_id", "speed", "num_lanes", "fec"],
-            "additionalProperties": false,
-            "properties": {
-                "logical_id": {
-                    "type": "integer",
-                    "description": "Logical port identifier for the management port."
-                },
-                "physical_id": {
-                    "type": "integer",
-                    "description": "Physical port identifier for the management port."
-                },
-                "speed": {
-                    "type": "integer",
-                    "description": "Default port speed in Mbps (e.g. 100000 for 100 GbE)."
-                },
-                "num_lanes": {
-                    "type": "integer",
-                    "description": "Number of physical lanes used by the management port."
-                },
-                "fec": {
-                    "type": "string",
-                    "description": "Forward Error Correction (FEC) mode (e.g. \"PC_FEC_RS528\")."
-                }
+            "type": "array",
+            "description": "Default settings for the management (out-of-band) ports, one entry per port.",
+            "minItems": 1,
+            "items": {
+                "$ref": "#/$defs/mgmt_port_settings"
             }
         },
         "preamble_support": {
@@ -208,5 +188,35 @@
                 "$ref": "https://github.com/facebook/fboss/blob/main/fboss/lib/asic_config_v3/schemas/conditional_setting.schema.json#/$defs/conditional_setting"
             }
         }
+    },
+    "$defs": {
+        "mgmt_port_settings": {
+            "type": "object",
+            "description": "Default settings for one management port.",
+            "required": ["logical_id", "physical_id", "speed", "num_lanes", "fec"],
+            "additionalProperties": false,
+            "properties": {
+                "logical_id": {
+                    "type": "integer",
+                    "description": "Logical port identifier for the management port."
+                },
+                "physical_id": {
+                    "type": "integer",
+                    "description": "Physical port identifier for the management port."
+                },
+                "speed": {
+                    "type": "integer",
+                    "description": "Default port speed in Mbps (e.g. 100000 for 100 GbE)."
+                },
+                "num_lanes": {
+                    "type": "integer",
+                    "description": "Number of physical lanes used by the management port."
+                },
+                "fec": {
+                    "type": "string",
+                    "description": "Forward Error Correction (FEC) mode (e.g. \"PC_FEC_RS528\")."
+                }
+            }
+        }
     }
 }