lotus-nexthop · Oct 22, 2026 · Oct 24, 2026 · Oct 25, 2026 · Oct 24, 2026 · Oct 2, 2026
@@ -11,6 +11,7 @@
     "ladakh800bcls",
     "m4061nhp",
     "m4062nhp",
+    "m4340nhp",
     "meru800bfa",
     "meru800bia",
     "minipack",

@@ -25,9 +25,9 @@ repos:
         # asic_config generated outputs carry no trailing newline by design.
         exclude: ^fboss/configs/platforms/[^/]+/[^/]+/asic_config/generated/
       - id: check-yaml
-        # asic_config generated outputs are multi-document YAML with complex
-        # mapping keys that PyYAML cannot load; they are generated artifacts.
-        exclude: ^fboss/configs/platforms/[^/]+/[^/]+/asic_config/generated/
+        # asic_config generated outputs and their synced references are
+        # multi-document YAML with complex mapping keys that PyYAML cannot load.
+        exclude: ^fboss/(configs/platforms/[^/]+/[^/]+/asic_config/generated|lib/asic_config_v2/synced_asic_configs)/
       - id: check-json
       - id: check-merge-conflict
   - repo: https://github.com/astral-sh/ruff-pre-commit

@@ -54,8 +54,8 @@ following fields.
 | `port_config` | XGS. Front-panel port settings: `default_speed` (in Mbps), `speed_to_fec` (mapping from speed to FEC mode), `enable` (the value emitted for `PC_PORT.ENABLE`), and `pc_port_overrides` (extra `PC_PORT` key/value lines emitted verbatim, for example `LINK_TRAINING`). This object is distinct from the DNX `port_config` string inside `asic_config_params`. |
 | `cpu_port` | XGS. CPU port settings: `speed` (in Mbps) and `num_lanes`. |
 | `mgmt_port` | XGS. Management port settings: `enabled` (whether the port is emitted at all), `enable` (the `PC_PORT.ENABLE` value), `in_port_block` (include the port in the `PORT` MTU range), and `speed_variants` (per-speed settings keyed by speed). |
-| `mgmt_port_overrides` | XGS. Platform overrides of the ASIC-level management port defaults: `logical_id`, `physical_id`, `speed`, `num_lanes`, and `fec`. |
-| `port_mapping_overrides` | XGS. Adjustments to the logical-to-physical port mapping formula: `core_range` (which cores participate, for example `"0-15,48-63"`), `num_lp_ports_on_even_core`, `num_logical_ports_per_datapath`, `lp_start_step_offset`, `lp_offset_simple`, `special_core_offset_apply_all`, and `exclude_logical_ports` (logical port IDs omitted from `PC_PORT_PHYS_MAP`, `PC_PORT`, and `PORT`, for front-panel ports that are not populated on the platform). |
+| `mgmt_port_overrides` | XGS. List of platform overrides of the ASIC-level management port defaults (`logical_id`, `physical_id`, `speed`, `num_lanes`, and `fec`), overriding the port at the same index. Entries beyond the defaults list declare additional ports and must be complete. Duplicate logical or physical port identifiers are rejected. |
+| `port_mapping_overrides` | XGS. Adjustments to the logical-to-physical port mapping formula: `core_range` (which cores participate, for example `"0-15,48-63"`), `num_lp_ports_on_even_core`, `num_logical_ports_per_datapath`, `lp_start_step_offset`, `lp_offset_simple`, and `exclude_logical_ports` (logical port IDs omitted from `PC_PORT_PHYS_MAP`, `PC_PORT`, and `PORT`, for front-panel ports that are not populated on the platform). |
 | `platform_sai_overrides` | XGS. Platform-level SAI settings. These take precedence within the layered `global` sources and override the ASIC-level SAI overrides. |
 | `platform_sdk_overrides` | DNX. Platform-level SOC properties applied on top of the ASIC `base_sdk_settings` and declarative tables. Keys carry their SOC suffix inline. |
 | `device_config_overrides` | XGS. Key/value pairs written to the `DEVICE_CONFIG` output table, for example clock frequencies. |
@@ -101,7 +101,7 @@ files under `fboss/configs/asic_vendors/broadcom/xgs/asics/`.
 | `port_architecture` | Core, lane, and datapath layout consumed by the port mapping logic: `num_cores`, `num_lanes_per_core`, `num_logical_ports_per_datapath`, `num_physical_ports_per_datapath`, and `num_lp_ports_on_even_core_default`. |
 | `mmu_size` | MMU buffer size in bytes. Also used as the `MAX_FRAME_SIZE` and port MTU values. |
 | `table_names` | Ordered list of output YAML table names. Controls which tables appear in the output and their order. |
-| `mgmt_port_defaults` | Default management port settings: `logical_id`, `physical_id`, `speed`, `num_lanes`, and `fec`. Platforms may override these per variant. |
+| `mgmt_port_defaults` | List of default management port settings, one entry per port: `logical_id`, `physical_id`, `speed`, `num_lanes`, and `fec`. Platforms may override these per variant. |
 | `preamble_support` | Whether the ASIC supports a preamble section prepended to the output YAML. When `false`, any `preamble_file` declared by a platform is ignored. |
 | `global_defaults` | ASIC-specific SDK settings copied into the `global` output table. |
 | `sai_overrides` | ASIC-specific SAI settings layered on top of the vendor SAI common values. |

@@ -275,6 +275,7 @@ int Platform::getLaneCount(cfg::PortProfileID profile) const {
     case cfg::PortProfileID::PROFILE_800G_8_PAM4_RS544X2N_OPTICAL:
     case cfg::PortProfileID::PROFILE_800G_8_PAM4_RS544X2N_COPPER:
     case cfg::PortProfileID::PROFILE_1600G_8_PAM4_RS544X2N_OPTICAL:
+    case cfg::PortProfileID::PROFILE_1600G_8_PAM4_RS544X2N_COPPER:
       return 8;
 
     case cfg::PortProfileID::PROFILE_DEFAULT:

@@ -166,6 +166,7 @@ uint16_t uplinksCountFromSwitch(PlatformType mode) {
     case PM::PLATFORM_ICECUBE800BC:
     case PM::PLATFORM_ICETEA800BC:
     case PM::PLATFORM_MONTBLANC:
+    case PM::PLATFORM_M4061NHP:
     case PM::PLATFORM_M4062NHP:
     case PM::PLATFORM_M5120CSC:
       return 4;
@@ -195,6 +196,7 @@ cfg::PortSpeed getPortSpeed(PlatformType platformType) {
       portSpeed = cfg::PortSpeed::TWOHUNDREDG;
       break;
     case PlatformType::PLATFORM_MONTBLANC:
+    case PlatformType::PLATFORM_M4061NHP:
       portSpeed = cfg::PortSpeed::FOURHUNDREDG;
       break;
     case PlatformType::PLATFORM_MINIPACK3N:

@@ -138,6 +138,8 @@ TEST(
       PlatformType::PLATFORM_M4062NHP,
       PlatformType::PLATFORM_M4061CLSC,
       PlatformType::PLATFORM_M5120CSC,
+      PlatformType::PLATFORM_M4340NHP,
+      PlatformType::PLATFORM_M4061NHP,
       futurePlatformType,
   };
   for (const auto type : platformTypes) {

@@ -199,6 +199,7 @@ enum PortProfileID {
   PROFILE_1600G_8_PAM4_RS544X2N_OPTICAL = 63,
   PROFILE_212POINT5G_1_PAM4_RS544X2N_OPTICAL = 64,
   PROFILE_212POINT5G_1_PAM4_RS544X2N_COPPER = 65,
+  PROFILE_1600G_8_PAM4_RS544X2N_COPPER = 66,
 }
 
 enum Scope {

@@ -110,6 +110,7 @@ cfg::PortSpeed getSpeed(cfg::PortProfileID profile) {
       return cfg::PortSpeed::EIGHTHUNDREDG;
 
     case cfg::PortProfileID::PROFILE_1600G_8_PAM4_RS544X2N_OPTICAL:
+    case cfg::PortProfileID::PROFILE_1600G_8_PAM4_RS544X2N_COPPER:
       return cfg::PortSpeed::ONEPOINTSIXT;
 
     case cfg::PortProfileID::PROFILE_DEFAULT:
@@ -151,6 +152,7 @@ TransmitterTechnology getMediaType(cfg::PortProfileID profile) {
     case cfg::PortProfileID::PROFILE_400G_2_PAM4_RS544X2N_COPPER:
     case cfg::PortProfileID::PROFILE_800G_4_PAM4_RS544X2N_COPPER:
     case cfg::PortProfileID::PROFILE_212POINT5G_1_PAM4_RS544X2N_COPPER:
+    case cfg::PortProfileID::PROFILE_1600G_8_PAM4_RS544X2N_COPPER:
       return TransmitterTechnology::COPPER;
 
     case cfg::PortProfileID::PROFILE_10G_1_NRZ_NOFEC_OPTICAL:

@@ -26,13 +26,15 @@
     "PC_PMD_FIRMWARE",
     "DLB_ECMP_CONFIG"
   ],
-  "mgmt_port_defaults": {
-    "logical_id": 76,
-    "physical_id": 513,
-    "speed": 100000,
-    "num_lanes": 4,
-    "fec": "PC_FEC_RS528"
-  },
+  "mgmt_port_defaults": [
+    {
+      "logical_id": 76,
+      "physical_id": 513,
+      "speed": 100000,
+      "num_lanes": 4,
+      "fec": "PC_FEC_RS528"
+    }
+  ],
   "preamble_support": true,
 
   "global_defaults": {

@@ -26,13 +26,15 @@
     "DLB_ECMP_CONFIG",
     "PHB_CONTROL"
   ],
-  "mgmt_port_defaults": {
-    "logical_id": 76,
-    "physical_id": 513,
-    "speed": 100000,
-    "num_lanes": 4,
-    "fec": "PC_FEC_RS528"
-  },
+  "mgmt_port_defaults": [
+    {
+      "logical_id": 76,
+      "physical_id": 513,
+      "speed": 100000,
+      "num_lanes": 4,
+      "fec": "PC_FEC_RS528"
+    }
+  ],
   "preamble_support": false,
 
   "global_defaults": {

@@ -28,10 +28,12 @@
       "enabled": true,
       "enable": 1
     },
-    "mgmt_port_overrides": {
-      "logical_id": 268,
-      "physical_id": 514
-    },
+    "mgmt_port_overrides": [
+      {
+        "logical_id": 268,
+        "physical_id": 514
+      }
+    ],
     "port_mapping_overrides": {
       "num_logical_ports_per_datapath": 16,
       "lp_start_step_offset": 2,

@@ -34,10 +34,12 @@
         }
       }
     },
-    "mgmt_port_overrides": {
-      "logical_id": 268,
-      "physical_id": 514
-    },
+    "mgmt_port_overrides": [
+      {
+        "logical_id": 268,
+        "physical_id": 514
+      }
+    ],
     "port_mapping_overrides": {
       "num_logical_ports_per_datapath": 18,
       "lp_start_step_offset": 0,

@@ -28,10 +28,12 @@
       "enabled": true,
       "enable": 1
     },
-    "mgmt_port_overrides": {
-      "logical_id": 268,
-      "physical_id": 514
-    },
+    "mgmt_port_overrides": [
+      {
+        "logical_id": 268,
+        "physical_id": 514
+      }
+    ],
     "port_mapping_overrides": {
       "num_logical_ports_per_datapath": 16,
       "lp_start_step_offset": 2,

@@ -30,10 +30,12 @@
       "enabled": true,
       "in_port_block": true
     },
-    "mgmt_port_overrides": {
-      "logical_id": 268,
-      "physical_id": 514
-    },
+    "mgmt_port_overrides": [
+      {
+        "logical_id": 268,
+        "physical_id": 514
+      }
+    ],
     "port_mapping_overrides": {
       "num_logical_ports_per_datapath": 18,
       "lp_start_step_offset": 0,

@@ -26,10 +26,12 @@
     "mgmt_port": {
       "enabled": true
     },
-    "mgmt_port_overrides": {
-      "logical_id": 268,
-      "physical_id": 514
-    },
+    "mgmt_port_overrides": [
+      {
+        "logical_id": 268,
+        "physical_id": 514
+      }
+    ],
     "port_mapping_overrides": {
       "num_logical_ports_per_datapath": 18,
       "lp_start_step_offset": 0,

@@ -0,0 +1,83 @@
+{
+  "platform_name": "m4061nhp",
+  "vendor": "broadcom",
+  "asic": "tomahawk6",
+  "num_ports_per_core": 1,
+  "defaults": {
+    "asic_config_params": {
+      "config_type": "YAML_CONFIG",
+      "exact_match": false,
+      "mmu_lossless": false,
+      "config_gen_type": "DEFAULT"
+    },
+    "port_config": {
+      "default_speed": 1600000,
+      "speed_to_fec": {
+        "400000": "PC_FEC_RS544_2XN",
+        "800000": "PC_FEC_RS544_2XN",
+        "1600000": "PC_FEC_RS544_2XN_IEEE"
+      }
+    },
+    "cpu_port": {
+      "speed": 10000,
+      "num_lanes": 1
+    },
+    "mgmt_port": {
+      "enabled": true
+    },
+    "mgmt_port_overrides": [
+      {
+        "logical_id": 268,
+        "physical_id": 514,
+        "speed": 100000,
+        "num_lanes": 4,
+        "fec": "PC_FEC_RS528"
+      }
+    ],
+    "port_mapping_overrides": {
+      "num_logical_ports_per_datapath": 17
+    },
+    "platform_sai_overrides": {
+      "pktio_mode": 1,
+      "vlan_flooding_l2mc_num_reserved": 0,
+      "shared_block_mask_section": "uc_bc",
+      "skip_protocol_default_entries": 1,
+      "sai_feat_tail_timestamp": 0,
+      "sai_port_phy_time_sync_en": 1,
+      "l3_intf_vlan_split_egress": 1,
+      "sai_stats_disable_mask": "0x200",
+      "l3_alpm_large_vrf_mode": 1,
+      "sai_ip_counter_cstats": 1,
+      "default_cpu_tx_queue": 7
+    },
+    "conditional_settings": [
+      {
+        "name": "m4061nhp_mmu_tables",
+        "condition": {
+          "source": "asic_config_params",
+          "param": "config_gen_type",
+          "equals": "DEFAULT"
+        },
+        "apply": {
+          "TM_THD_CONFIG": {
+            "MIRROR_ON_DROP_RESERVATION": 0,
+            "SKIP_BUFFER_RESERVATION": 1
+          }
+        },
+        "skip_from_sai_common": [
+          "sai_optimized_mmu",
+          "sai_mmu_qgroups_default"
+        ]
+      }
+    ],
+    "features": {
+      "generate_dlb_config": true,
+      "generate_dlb_ecmp_config": true,
+      "generate_low_clock_freq_settings": false,
+      "generate_autoload_board_settings": true
+    }
+  },
+  "variants": {
+    "default": {}
+  }
+}