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commit 219af5dfce98fe254335ea79c2bf98428c38370c upstream.
Use model-specific configuration data for the number of memory controllers
per socket, channels per memory controller, and DIMMs per channel as
intended, instead of relying on global macros for maximum values.
No functional changes intended.
Intel-SIG: commit 219af5dfce98 EDAC/{skx_common,skx}: Use configuration data, not global macros
Backport EDAC for DMR
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20250731145534.2759334-2-qiuxu.zhuo@intel.com
[ Zhang Rui: amend change log ]
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
commit 59cfc06a874e01633865d0b05eba47b09b8b3a8f upstream. The mc_mapping and imc fields of struct skx_dev have the same size, NUM_IMC. Move mc_mapping to be a field inside struct skx_imc to prepare for making the imc array of memory controller instances a flexible array. No functional changes intended. Intel-SIG: commit 59cfc06a874e EDAC/skx_common: Move mc_mapping to be a field inside struct skx_imc Backport EDAC for DMR Suggested-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20250731145534.2759334-3-qiuxu.zhuo@intel.com [ Zhang Rui: amend change log ] Signed-off-by: Zhang Rui <rui.zhang@intel.com>
commit 30b47b71fdc0091db5a4fa9503ad630aeb0ab3eb upstream.
The current mapping of memory controller indices is from physical index [1]
to logical index [2], as show below:
skx_dev->imc[pmc].mc_mapping = lmc
Since skx_dev->imc[] is an array of present memory controller instances,
mapping memory controller indices from logical index to physical index,
as show below, is more reasonable. This is also a preparatory step for
making skx_dev->imc[] a flexible array.
skx_dev->imc[lmc].mc_mapping = pmc
Both mappings are equivalent. No functional changes intended.
[1] Indices for memory controllers include both those present to the
OS and those disabled by BIOS.
[2] Indices for memory controllers present to the OS.
Intel-SIG: commit 30b47b71fdc0 EDAC/skx_common: Swap memory controller index mapping
Backport EDAC for DMR
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20250731145534.2759334-4-qiuxu.zhuo@intel.com
[ Zhang Rui: amend change log ]
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
commit 43060ca5332462903f57c2ff9b49b69124618070 upstream. The current skx->imc[NUM_IMC] array of memory controller instances is sized using the macro NUM_IMC. Each time EDAC support is added for a new CPU, NUM_IMC needs to be updated to ensure it is greater than or equal to the number of memory controllers for the new CPU. This approach is inconvenient and results in memory waste for older CPUs with fewer memory controllers. To address this, make skx->imc[] a flexible array and determine its size from configuration data or at runtime. Intel-SIG: commit 43060ca53324 EDAC/skx_common: Make skx_dev->imc[] a flexible array Backport EDAC for DMR Suggested-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20250731145534.2759334-5-qiuxu.zhuo@intel.com [ Zhang Rui: amend change log ] Signed-off-by: Zhang Rui <rui.zhang@intel.com>
…ci_dev
commit b3d70059cbb262eef12927dbcf37ba8586d4a3ab upstream.
Memory controllers in the new Intel server CPUs, such as Diamond Rapids,
are presented as MMIO-based devices rather than PCI devices.
Modify skx_register_mci() to be independent of 'pci_dev' and use a generic
'dev' of 'struct device' to prepare for support of such MMIO-based memory
controllers.
Intel-SIG: commit b3d70059cbb2 EDAC/{skx_common,skx,i10nm}: Make skx_register_mci() independent of pci_dev
Backport EDAC for DMR
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://patch.msgid.link/20251119134132.2389472-2-qiuxu.zhuo@intel.com
[ Zhang Rui: amend change log ]
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
commit 9529e697739e2d4dc8c4129bbe91576f744f79f6 upstream.
The Intel EDAC library 'skx_common' maintains the Intel server EDAC device
list for {skx, i10nm}_edac drivers, which use skx_get_all_bus_mappings()
to build and retrieve the EDAC device list.
However, the upcoming Intel EDAC driver, imh_edac, for Diamond Rapids
servers is designed for memory controllers that are MMIO-based devices
rather than PCI devices. Consequently, it can't use
skx_get_all_bus_mappings() due to the absence of a PCI bus. To accommodate
this, prepare skx_get_edac_list() to enable the upcoming imh_edac driver
to obtain the EDAC device list from the skx_common library and build the
EDAC device list independently.
Intel-SIG: commit 9529e697739e EDAC/skx_common: Prepare for skx_get_edac_list()
Backport EDAC for DMR
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://patch.msgid.link/20251119134132.2389472-3-qiuxu.zhuo@intel.com
[ Zhang Rui: amend change log ]
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
commit d4839582bc7002095b013acb4a2dcaa1438c41aa upstream. The upcoming imh_edac driver for Intel Diamond Rapids servers cannot use skx_get_hi_lo() in skx_common to retrieve the TOHM (Top of High Memory) and TOLM (Top of Low Memory) parameters. Instead, it obtains these parameters within its own EDAC driver. To accommodate this, prepare skx_set_hi_lo() to allow the driver to notify skx_common of these parameters. Intel-SIG: commit d4839582bc70 EDAC/skx_common: Prepare for skx_set_hi_lo() Backport EDAC for DMR Tested-by: Yi Lai <yi1.lai@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20251119134132.2389472-4-qiuxu.zhuo@intel.com [ Zhang Rui: amend change log ] Signed-off-by: Zhang Rui <rui.zhang@intel.com>
commit 9fc67b11703fe9d8a5617ccacec2a452e455fa52 upstream.
Intel Diamond Rapids CPUs include Integrated Memory and I/O Hubs (IMH).
The memory controllers within the IMHs provide memory stacks to the
processor. Create a new driver for this IMH-based memory controllers
rather than applying additional patches to the existing i10nm_edac.c
for the following reasons:
1) The memory controllers are not presented as PCI devices; instead,
the detection and all their registers have been transitioned to
MMIO-based memory spaces.
2) Validation processes are costly. Modifications to i10nm_edac would
require extensive validation checks against multiple platforms,
including Ice Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids,
Sierra Forest, and Grand Ridge.
3) Future Intel CPUs will likely only need patches on top of this new
EDAC driver. Validation can be limited to Diamond Rapids servers
and future Intel CPU generations.
[Tony: Fix kerneldoc for struct local_reg]
[randconfig: Added dependencies on NFIT and DMI]
Intel-SIG: commit 9fc67b11703f EDAC/{skx_common,imh}: Add EDAC driver for Intel Diamond Rapids servers
Backport EDAC for DMR
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://patch.msgid.link/20251119134132.2389472-5-qiuxu.zhuo@intel.com
[ Zhang Rui: amend change log ]
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
commit 39abdcbdad597b1ac3dabd44a757de91b87c683a upstream. The allowed maximum number of row bits for DRAM chips in the Diamond Rapids server processor is up to 19. Extend the current maximum row bits from 18 to 19. Intel-SIG: commit 39abdcbdad59 EDAC/skx_common: Extend the maximum number of DRAM chip row bits Backport EDAC for DMR Tested-by: Yi Lai <yi1.lai@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20251119134132.2389472-6-qiuxu.zhuo@intel.com [ Zhang Rui: amend change log ] Signed-off-by: Zhang Rui <rui.zhang@intel.com>
commit f619613f3058dee38f50b116ec774c5295c8b08b upstream.
Detect 2-level memory configurations and notify the 'skx_common' library
to enable ADXL 2-level memory error decoding.
Intel-SIG: commit f619613f3058 EDAC/{skx_comm,imh}: Detect 2-level memory configuration
Backport EDAC for DMR
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://patch.msgid.link/20251119134132.2389472-7-qiuxu.zhuo@intel.com
[ Zhang Rui: amend change log ]
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
commit 5f40ea7f41773d996d92db8bde600199200adc11 upstream. Setup the following debugfs testing node to enable fake memory error address decoding tests for the imh_edac driver. /sys/kernel/debug/edac/imh_test/addr Intel-SIG: commit 5f40ea7f4177 EDAC/imh: Setup 'imh_test' debugfs testing node Backport EDAC for DMR Tested-by: Yi Lai <yi1.lai@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20251119134132.2389472-8-qiuxu.zhuo@intel.com [ Zhang Rui: amend change log ] Signed-off-by: Zhang Rui <rui.zhang@intel.com>
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Backport EDAC support for DMR
New config:
CONFIG_EDAC_IMH=m
Test:
Tested on DMR,
The EDAC driver can be loaded, and the CE/UE are correctly triggered and logged by kernel.
1/11: EDAC/{skx_common,skx}: Use configuration data, not global macros
2/11: EDAC/skx_common: Move mc_mapping to be a field inside struct skx_imc
3/11: EDAC/skx_common: Swap memory controller index mapping
4/11: EDAC/skx_common: Make skx_dev->imc[] a flexible array
5/11: EDAC/{skx_common,skx,i10nm}: Make skx_register_mci() independent of pci_dev
6/11: EDAC/skx_common: Prepare for skx_get_edac_list()
7/11: EDAC/skx_common: Prepare for skx_set_hi_lo()
8/11: EDAC/{skx_common,imh}: Add EDAC driver for Intel Diamond Rapids servers
9/11: EDAC/skx_common: Extend the maximum number of DRAM chip row bits
10/11: EDAC/{skx_comm,imh}: Detect 2-level memory configuration
11/11: EDAC/imh: Setup 'imh_test' debugfs testing node