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flow: remove seven-layer stack from Cockpit Full Flow #351: Commit b301ef4 pushed by phsauter
2h 24m 53s main
main
2h 24m 53s
klayout: add DRC setup and include in CI Full Flow #350: Pull request #134 synchronize by phsauter
1h 47m 48s phsauter/klayout-drc-lvs
phsauter/klayout-drc-lvs
1h 47m 48s
klayout: add DRC setup and include in CI Full Flow #349: Pull request #134 synchronize by phsauter
2h 23m 21s phsauter/klayout-drc-lvs
phsauter/klayout-drc-lvs
2h 23m 21s
klayout: add DRC setup and include in CI Full Flow #348: Pull request #134 synchronize by phsauter
3h 0m 41s phsauter/klayout-drc-lvs
phsauter/klayout-drc-lvs
3h 0m 41s
klayout: add DRC setup and include in CI Full Flow #347: Pull request #134 synchronize by phsauter
3h 0m 49s phsauter/klayout-drc-lvs
phsauter/klayout-drc-lvs
3h 0m 49s
klayout: add DRC setup and include in CI Full Flow #346: Pull request #134 synchronize by phsauter
3h 0m 31s phsauter/klayout-drc-lvs
phsauter/klayout-drc-lvs
3h 0m 31s
klayout: add DRC setup and include in CI Full Flow #345: Pull request #134 opened by phsauter
3h 0m 58s phsauter/klayout-drc-lvs
phsauter/klayout-drc-lvs
3h 0m 58s
ci: test RTL and post-Yosys simulations Full Flow #344: Commit 968bab1 pushed by phsauter
2h 8m 48s main
main
2h 8m 48s
Rework PDK handling and add post-synthesis simulation Full Flow #343: Pull request #132 synchronize by phsauter
2h 7m 40s phsauter/cmos5l
phsauter/cmos5l
2h 7m 40s
Rework PDK handling and add post-synthesis simulation Full Flow #342: Pull request #132 synchronize by phsauter
2h 19m 3s phsauter/cmos5l
phsauter/cmos5l
2h 19m 3s
Rework PDK handling and add post-synthesis simulation Full Flow #341: Pull request #132 synchronize by phsauter
1h 23m 38s phsauter/cmos5l
phsauter/cmos5l
1h 23m 38s
Rework PDK handling and add post-synthesis simulation Full Flow #340: Pull request #132 synchronize by phsauter
2h 11m 11s phsauter/cmos5l
phsauter/cmos5l
2h 11m 11s
xilinx: Add support for Digilent Basys3 board (#130) Full Flow #339: Commit 511f5fa pushed by phsauter
1h 4m 15s main
main
1h 4m 15s
xilinx: Add support for Digilent Basys3 board Full Flow #338: Pull request #130 synchronize by FrancescoConti
1h 6m 13s FrancescoConti:main
FrancescoConti:main
1h 6m 13s
Rework PDK handling and add post-synthesis simulation Full Flow #337: Pull request #132 synchronize by phsauter
2h 2m 59s phsauter/cmos5l
phsauter/cmos5l
2h 2m 59s
Rework PDK handling and add post-synthesis simulation Full Flow #336: Pull request #132 synchronize by phsauter
2h 9m 22s phsauter/cmos5l
phsauter/cmos5l
2h 9m 22s
Rework PDK handling and add post-synthesis simulation Full Flow #335: Pull request #132 synchronize by phsauter
2h 8m 27s phsauter/cmos5l
phsauter/cmos5l
2h 8m 27s
Rework PDK handling and add post-synthesis simulation Full Flow #334: Pull request #132 synchronize by phsauter
2h 6m 1s phsauter/cmos5l
phsauter/cmos5l
2h 6m 1s
Rework PDK handling and add post-synthesis simulation Full Flow #333: Pull request #132 synchronize by phsauter
2h 3m 56s phsauter/cmos5l
phsauter/cmos5l
2h 3m 56s
Rework PDK handling and add post-synthesis simulation Full Flow #332: Pull request #132 synchronize by phsauter
2h 6m 29s phsauter/cmos5l
phsauter/cmos5l
2h 6m 29s
Rework PDK handling and add post-synthesis simulation Full Flow #331: Pull request #132 synchronize by phsauter
2h 15m 14s phsauter/cmos5l
phsauter/cmos5l
2h 15m 14s
Rework PDK handling and add post-synthesis simulation Full Flow #330: Pull request #132 synchronize by phsauter
2h 4m 1s phsauter/cmos5l
phsauter/cmos5l
2h 4m 1s
Rework PDK handling and add post-synthesis simulation Full Flow #329: Pull request #132 synchronize by phsauter
2h 10m 42s phsauter/cmos5l
phsauter/cmos5l
2h 10m 42s
Rework PDK handling and add post-synthesis simulation Full Flow #328: Pull request #132 synchronize by phsauter
2h 7m 22s phsauter/cmos5l
phsauter/cmos5l
2h 7m 22s
Rework PDK handling and add post-synthesis simulation Full Flow #327: Pull request #132 synchronize by phsauter
2h 8m 54s phsauter/cmos5l
phsauter/cmos5l
2h 8m 54s