Cphy rb3g2 rb4 rb8 by aarunnan · Pull Request #767 · qualcomm-linux/kernel

aarunnan · 2026-06-24T01:35:28Z

CPHY changes for RB3G2, RB4 and RB8.
CRs-Fixed: 4571838

aarunnan · 2026-06-24T18:52:42Z

JIRA ticket - https://jira-dc.qualcomm.com/jira/browse/QLIJIRA-143

sgaud-quic · 2026-06-25T05:00:14Z

Rebase the PR on tip, dont merge the branch onto PR

Read PHY configuration from the device-tree bus-type and save it into the csiphy structure for later use. For C-PHY, skip clock line configuration, as there is none. Link: https://lore.kernel.org/all/20260301-qcom-cphy-v4-1-e53316d2cc65@ixit.cz/ Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

…g C-PHY lanes So far, only D-PHY mode was supported, which uses even bits when enabling or masking lanes. For C-PHY configuration, the hardware instead requires using the odd bits. Since there can be unrecognized configuration allow returning failure. Link: https://lore.kernel.org/r/20260301-qcom-cphy-v4-2-e53316d2cc65@ixit.cz/ Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

Inherit C-PHY information from CSIPHY, so we can configure CSID properly. CSI2_RX_CFG0_PHY_TYPE_SEL must be set to 1, when C-PHY mode is used. Link: https://lore.kernel.org/r/20260301-qcom-cphy-v4-3-e53316d2cc65@ixit.cz Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

…on is available The lanes must not be initialized before the driver has access to the lane configuration, as it depends on whether D-PHY or C-PHY mode is in use. Move the lane initialization to a later stage where the configuration structures are available. Link: https://lore.kernel.org/r/20260301-qcom-cphy-v4-4-e53316d2cc65@ixit.cz Signed-off-by: Petr Hodina <phodina@protonmail.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

…HY init Add a PHY configuration sequence for the sdm845 which uses a Qualcomm Gen 2 version 1.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports three-phase C-PHY mode. Link: https://lore.kernel.org/r/20260301-qcom-cphy-v4-5-e53316d2cc65@ixit.cz/ Signed-off-by: Casey Connolly <casey.connolly@linaro.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Co-developed-by: David Heidelberg <david@ixit.cz> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

… CPHY init These values should improve C-PHY behaviour. Should match most recent Qualcomm code. Link: https://lore.kernel.org/r/20260301-qcom-cphy-v4-6-e53316d2cc65@ixit.cz/ Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

…C-PHY init Add a PHY configuration sequence for the sm8250 which uses a Qualcomm Gen 2 version 1.2.1 CSI-2 PHY. The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports three-phase C-PHY mode. Link: https://lore.kernel.org/r/20260301-qcom-cphy-v4-7-e53316d2cc65@ixit.cz/ Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

@BoD

…uration Catch when C-PHY configuration gets used on SoC with CAMSS missing C-PHY configuration lane registers. Hopefully this check will disappear as these lane regs gets populated. -- @BoD Proliferating special cases in switch statements on a per-SoC basis is verboten. Please find another way to do this, you already have a bool to indicate cphy in struct csid_phy_config {} so at some level CAMSS already has a bool to indicate what to do. Please make that logic accessible to logical consumers throughout, in this case the CPHY code. -- Link: https://lore.kernel.org/r/20260301-qcom-cphy-v4-8-e53316d2cc65@ixit.cz Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

… frequency Ensure that the link frequency divider correctly accounts for C-PHY operation. The divider differs between D-PHY and C-PHY, as described in the MIPI CSI-2 specification. For more details, see: https://docs.kernel.org/driver-api/media/tx-rx.html#pixel-rate Link: https://lore.kernel.org/r/20260301-qcom-cphy-v4-9-e53316d2cc65@ixit.cz Suggested-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

Use these switch cases to add the sa8775p (CAMSS_8775P) 3-phase 1.5 Gsps settings, programming the appropriate common-control register 5/6/7 and reset-release values for C-PHY and D-PHY. CRs-Fixed: 4571838 Signed-off-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

Add the CSI2 RX PHY type select bitfield and program it from the configured PHY type so that the CSID RX path is told whether the incoming data is C-PHY or D-PHY. CRs-Fixed: 4571838 Signed-off-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

Add the lane_regs_sa8775p_3ph[] register table for the sa8775p Gen3 CSIPHY at 1.5 Gsps, and select it in csiphy_lanes_enable() for CAMSS_8775P when the endpoint is configured for C-PHY, falling back to the existing sa8775p D-PHY table otherwise. CRs-Fixed: 4571838 Signed-off-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

Share the C-PHY/D-PHY lane_regs selection for CAMSS_8300 so the sa8300 platform uses the same 3ph handling as CAMSS_8775P. Also drop CAMSS_8300 from the missing-C-PHY-table guard now that a C-PHY table is provided. CRs-Fixed: 4571838 Signed-off-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

…r settings The C-PHY PHY register configuration needs to vary with the link (symbol) data rate. Until now only a single base lane_regs table was applied per platform, regardless of the negotiated rate. Introduce a data-rate selection mechanism for C-PHY: - Add struct data_rate_reg_info describing a per-bandwidth register override table. - Add csiphy_cphy_data_rate_config(), which selects the first table entry whose bandwidth satisfies the required PHY data rate (derived from the resolved link frequency) and writes those overrides on top of the base lane_regs configuration. The settle-count parameter types are handled specially. When the link frequency cannot be resolved, it falls back to the lowest supported rate. - Add per-data-rate register tables and data_rate_settings tables for sa8775p and 8300(1.5/1.7/2.5/3.5/4.5 GSpS) and sm8250 (2.5/3.5/4.5 GSpS). - Select the appropriate data-rate settings table in csiphy_lanes_enable() for both platforms when the endpoint is configured for C-PHY. CRs-Fixed: 4571838 Co-developed-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

Parse the remote (sensor) endpoint in camss_parse_endpoint_node() and compare its bus-type against the local (CSIPHY) endpoint. Reject the link with -EINVAL if the two ends disagree, so CPHY/DPHY mismatches are caught early during probe. CRs-Fixed: 4571838 Co-developed-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Jigarkumar Zala <jzala@qti.qualcomm.com> Signed-off-by: Anusha Arun Nandi <aarunnan@qti.qualcomm.com>

Signed-off-by: aarunnan <aarunnan@quicinc.com>

qlijarvis · 2026-06-25T17:52:45Z

PR #767 — validate-patch

PR: #767

Verdict	Issues	Detailed Report
⚠️	0	Full report

Final Summary

Lore link present: Yes for FROMLIST (01-09), No for PENDING (10-15) — correct per policy
Lore link matches PR commits: Cannot verify — lore series dated 2026-03-01 is not accessible as of 2026-06-25
Upstream patch status: Unknown — cannot check lore.kernel.org due to future-dated links
PR present in qcom-next: Not checked — validation scope limited to commit message and diff correctness per instructions

Verdict: ⚠️ — click to expand

🔍 Patch Validation

PR: #767 - C-PHY support for Qualcomm CAMSS driver
Upstream commit: Multiple patches from lore series 20260301-qcom-cphy-v4
Verdict: ⚠️ PARTIAL

Summary

This PR contains 15 commits split into two categories:

9 FROMLIST commits (patches 01-09): Upstream patches from lore.kernel.org series

6 PENDING commits (patches 10-15): Vendor-specific additions not yet posted upstream

FROMLIST Commits (01-09) - Upstream Backports

Patch Subject Author Lore Link Status

01/15 csiphy: Introduce PHY configuration David Heidelberg ✅ Present ⚠️ Future date

02/15 csiphy-3ph: Use odd bits for C-PHY lanes David Heidelberg ✅ Present ⚠️ Future date

03/15 Prepare CSID for C-PHY support David Heidelberg ✅ Present ⚠️ Future date

04/15 Initialize lanes after config available Petr Hodina ✅ Present ⚠️ Future date

05/15 csiphy-3ph: Add Gen2 v1.1 CPHY init Casey Connolly ✅ Present ⚠️ Future date

06/15 csiphy-3ph: Update Gen2 v1.2 David Heidelberg ✅ Present ⚠️ Future date

07/15 csiphy-3ph: Add Gen2 v2.0 Luca Weiss ✅ Present ⚠️ Future date

08/15 csiphy-3ph: C-PHY needs 3 lanes David Heidelberg ✅ Present ⚠️ Future date

09/15 Account for C-PHY when calculating David Heidelberg ✅ Present ⚠️ Future date

FROMLIST Commit Message Validation:

Check Status Note

Subject format ✅ PASS All follow "media: qcom: camss: : "

Body preserves rationale ✅ PASS Technical rationale present in all commits

Link tag present ✅ PASS All 9 commits have lore.kernel.org links

Link format ✅ PASS Proper Link: tag format used

Authorship preserved ✅ PASS Original authors maintained in From: field

Sign-off chain ✅ PASS Original author SoB + Anusha Arun Nandi SoB

Co-developed-by ✅ PASS Properly used in patch 05/15 (Casey + David)

Reviewed-by tags ✅ PASS Preserved in patches 05/15 and 07/15

FROMLIST Diff Validation:

Cannot verify diff faithfulness because the lore links reference future dates (2026-03-01), which don't exist yet. The series 20260301-qcom-cphy-v4 is not accessible on lore.kernel.org as of 2026-06-25.

⚠️ Issue: The lore links point to patches dated 2026-03-01, but this PR is dated 2026-06-09. This suggests either:

The patches were posted to the mailing list in March 2026 and are being backported now, OR

The lore links are placeholders for a series that will be posted later

PENDING Commits (10-15) - Vendor-Specific

Patch Subject Author CRs-Fixed Status

10/15 Program common control registers Jigarkumar Zala 4571838 ✅ Vendor

11/15 Prepare CSID for C-PHY support (Gen3) Jigarkumar Zala 4571838 ✅ Vendor

12/15 Add sa8775p C-PHY 3ph lane regs Jigarkumar Zala 4571838 ✅ Vendor

13/15 Add CAMSS_8300 C-PHY support Anusha Arun Nandi 4571838 ✅ Vendor

14/15 Dynamic data-rate specific C-PHY regs Anusha Arun Nandi 4571838 ✅ Vendor

15/15 Validate local/remote endpoint bus-type Anusha Arun Nandi 4571838 ✅ Vendor

PENDING Commit Message Validation:

Check Status Note

Subject format ✅ PASS All follow "media: qcom: camss: "

Body preserves rationale ✅ PASS Technical rationale present

CRs-Fixed tag ✅ PASS All 6 commits have CRs-Fixed: 4571838

Authorship ✅ PASS Jigarkumar Zala (10-12), Anusha Arun Nandi (13-15)

Sign-off chain ✅ PASS Proper SoB chains maintained

Co-developed-by ✅ PASS Properly used in patches 14/15 and 15/15

No lore links ✅ PASS Correctly omitted (vendor-only)

PENDING Diff Validation:

These are vendor-specific enhancements not posted upstream:

Patch 10: Adds common control register programming for C-PHY

Patch 11: Extends CSID Gen3 support for C-PHY

Patch 12: Adds sa8775p-specific C-PHY register tables

Patch 13: Enables CAMSS_8300 to share sa8775p C-PHY configuration

Patch 14: Implements data-rate-specific register overrides for C-PHY (1.5/1.7/2.5/3.5/4.5 GSpS)

Patch 15: Adds endpoint bus-type validation to catch CPHY/DPHY mismatches early

All changes are additive and platform-specific, appropriate for PENDING status.

Issues

⚠️ Critical Issue: Unverifiable Lore Links

Problem: All 9 FROMLIST patches reference lore links dated 2026-03-01, but the PR is dated 2026-06-09. The lore series 20260301-qcom-cphy-v4-*-e53316d2cc65@ixit.cz cannot be fetched from lore.kernel.org.

Impact: Cannot verify:

Whether the PR diffs match the upstream patches

Whether the upstream patches have been accepted/merged

Whether commit messages match upstream versions

Recommendation:

If the series was already posted in March 2026, verify the lore links are accessible

If the series will be posted later, update the FROMLIST prefix to PENDING until upstream posting is complete

Once posted, verify each patch diff matches the upstream version exactly

✅ No Other Issues Found

Commit message format is correct for both FROMLIST and PENDING commits

Authorship chains are properly maintained

Sign-off-by chains follow kernel conventions

Co-developed-by tags are used correctly

CRs-Fixed tags present on all PENDING commits

No QCLINUX-style vendor commits mixed in

Subject lines follow subsystem conventions

Verdict

Cannot fully validate due to inaccessible lore links. The commit messages and structure are correct, but diff faithfulness cannot be verified.

Recommendation:

✅ Merge PENDING commits (10-15) — These are vendor-specific and properly formatted

⚠️ Hold FROMLIST commits (01-09) until lore links are verified accessible and diffs are confirmed to match upstream

Final Summary

Lore link present: Yes for FROMLIST (01-09), No for PENDING (10-15) — correct per policy

Lore link matches PR commits: Cannot verify — lore series dated 2026-03-01 is not accessible as of 2026-06-25

Upstream patch status: Unknown — cannot check lore.kernel.org due to future-dated links

PR present in qcom-next: Not checked — validation scope limited to commit message and diff correctness per instructions

qlijarvis · 2026-06-25T17:52:47Z

PR #767 — checker-log-analyzer

PR: #767
Checker run: https://github.com/qualcomm-linux/kernel-config/actions/runs/28186657762

Checker	Result	Summary
Checker	Result	Summary
checkpatch	✅	All 15 commits passed
dt-binding-check	⏭️	Skipped - no DT binding changes
dtb-check	⏭️	Skipped - no devicetree changes
sparse-check	✅	Passed (pre-existing warnings in nouveau driver only)
check-uapi-headers	✅	No UAPI header changes
check-patch-compliance	❌	10 commits failed validation
tag-check	N/A	Not applicable for this branch
qcom-next-check	⚠️	FROMLIST commits present (expected)

Detailed report: Full report

Checker analysis — click to expand

🤖 CI Checker Analysis (checker-log-analyzer)

PR: #767 - media: qcom: camss: C-PHY support series (15 commits)
Source: https://github.com/qualcomm-linux/kernel-config/actions/runs/28186657762

Checker Result Summary

checkpatch ✅ All 15 commits passed

dt-binding-check ⏭️ Skipped - no DT binding changes

dtb-check ⏭️ Skipped - no devicetree changes

sparse-check ✅ Passed (pre-existing warnings in nouveau driver only)

check-uapi-headers ✅ No UAPI header changes

check-patch-compliance ❌ 10 commits failed validation

tag-check N/A Not applicable for this branch

qcom-next-check ⚠️ FROMLIST commits present (expected)

❌ check-patch-compliance

Root cause: Two distinct compliance violations across 10 commits

Failure details:

Issue 1: FROMLIST patches don't match upstream (4 commits)
Checking commit: FROMLIST: media: qcom: camss: Prepare CSID for C-PHY support
Change is different from the one mentioned in Link

Checking commit: FROMLIST: media: qcom: camss: Initialize lanes after lane configuration is available
Change is different from the one mentioned in Link

Checking commit: FROMLIST: media: qcom: camss: csiphy-3ph: C-PHY needs own lane configuration
Change is different from the one mentioned in Link

Checking commit: FROMLIST: media: qcom: camss: Account for C-PHY when calculating link frequency
Change is different from the one mentioned in Link
Issue 2: PENDING commits missing required prefix (6 commits)
Checking commit: PENDING: media: qcom: camss: Program common control register
Commit summary does not start with a required prefix

Checking commit: PENDING: media: qcom: camss: Prepare CSID for C-PHY support in gen3
Commit summary does not start with a required prefix

Checking commit: PENDING: media: qcom: camss: Add sa8775p C-PHY 3ph lane config
Commit summary does not start with a required prefix

Checking commit: PENDING: media: qcom: camss: Add CAMSS_8300 C-PHY support
Commit summary does not start with a required prefix

Checking commit: PENDING: media: qcom: camss: Dynamic data-rate specific C-PHY register settings
Commit summary does not start with a required prefix

Checking commit: PENDING: media: qcom: camss: validate local/remote endpoint bus-type
Commit summary does not start with a required prefix
Fix:

For Issue 1 (FROMLIST mismatch):
The 4 FROMLIST commits have diverged from their upstream lore.kernel.org versions. You must either:

Rebase/update the commits to match the exact upstream patches from the Link: tags, OR

Change prefix from FROMLIST: to PENDING: if these are modified versions not yet upstream

To verify which patches differ:
# For each failing commit, compare with upstream
git show <commit-sha> > local.patch
b4 am <lore-link-from-commit-message>
diff local.patch <downloaded-patch>
For Issue 2 (PENDING prefix):
The 6 PENDING commits need a subsystem-specific prefix. Based on the file paths (drivers/media/platform/qcom/camss/), use:
PENDING: media: qcom: camss: <description>
should become:
media: qcom: camss: <description>
OR if truly pending upstream submission:
FROMGIT: media: qcom: camss: <description>
The checker expects commits to follow Qualcomm's tagging policy:

UPSTREAM: - merged in mainline

FROMLIST: - posted to mailing list, exact match required

FROMGIT: - in maintainer tree, not yet in mainline

BACKPORT: - backported with modifications

No prefix for Qualcomm-specific changes

Reproduce locally:
cd /path/to/kernel
git fetch origin pull/767/head:pr-767
git checkout pr-767
bash ../kernel-checkers/check-patch-compliance.sh \
  --kernel-src . \
  --base c9744addfb04eec214121e1fc11040e828576da4 \
  --head 2720b272572a75c103ee568800ccff22ed2b860f
Verdict

10 blockers must be fixed before merge:

4 FROMLIST commits need to match their upstream versions exactly or be re-tagged

6 PENDING commits need proper subject prefixes per Qualcomm kernel policy

All other checkers passed successfully. Once commit compliance is resolved, this PR will be ready to merge.

qcomlnxci requested review from a team, idlethread, jingyiwang42 and mukeshojha-linux June 24, 2026 01:36

aarunnan force-pushed the cphy_rb3g2_rb4_rb8 branch from 6e5c140 to a1c2650 Compare June 24, 2026 05:51

aarunnan marked this pull request as ready for review June 24, 2026 18:52

okias and others added 15 commits June 25, 2026 09:46

aarunnan force-pushed the cphy_rb3g2_rb4_rb8 branch from f3d9d9d to adb6a91 Compare June 25, 2026 16:53

Merge branch 'qcom-6.18.y' into cphy_rb3g2_rb4_rb8

2720b27

Signed-off-by: aarunnan <aarunnan@quicinc.com>

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Cphy rb3g2 rb4 rb8#767

Cphy rb3g2 rb4 rb8#767
aarunnan wants to merge 16 commits into
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aarunnan commented Jun 24, 2026

Uh oh!

aarunnan commented Jun 24, 2026

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sgaud-quic commented Jun 25, 2026

Uh oh!

qlijarvis commented Jun 25, 2026

🔍 Patch Validation

Summary

FROMLIST Commits (01-09) - Upstream Backports

PENDING Commits (10-15) - Vendor-Specific

Issues

⚠️ Critical Issue: Unverifiable Lore Links

✅ No Other Issues Found

Verdict

Final Summary

Uh oh!

qlijarvis commented Jun 25, 2026

🤖 CI Checker Analysis (checker-log-analyzer)

❌ check-patch-compliance

Verdict

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aarunnan commented Jun 24, 2026

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aarunnan commented Jun 24, 2026

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sgaud-quic commented Jun 25, 2026

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qlijarvis commented Jun 25, 2026

PR #767 — validate-patch

Final Summary

🔍 Patch Validation

Summary

FROMLIST Commits (01-09) - Upstream Backports

PENDING Commits (10-15) - Vendor-Specific

Issues

⚠️ Critical Issue: Unverifiable Lore Links

✅ No Other Issues Found

Verdict

Final Summary

Uh oh!

qlijarvis commented Jun 25, 2026

PR #767 — checker-log-analyzer

🤖 CI Checker Analysis (checker-log-analyzer)

❌ check-patch-compliance

Verdict

Uh oh!

Reviewers

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Development

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8 participants