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sscs-ose
sscs-ose-code-a-chip.github.io
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[ISSCC27 Submission] RV32I Processor with AXI4-Lite Interconnect & 4x Scaled VGA Subsystem on SkyWater 130nm
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[ISSCC27 Submission] RV32I Processor with AXI4-Lite Interconnect & 4x Scaled VGA Subsystem on SkyWater 130nm
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[ISSCC27 Submission] RV32I Processor with AXI4-Lite Interconnect & 4x Scaled VGA Subsystem on SkyWater 130nm
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[ISSCC27 Submission] RV32I Processor with AXI4-Lite Interconnect & 4x Scaled VGA Subsystem on SkyWater 130nm
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ISSCC27: Measuring the design decisions of an open-source post-quantum HSM chip — ML-KEM-512 NTT and Keccak from Python golden model to SKY130 layout
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ISSCC27: Measuring the design decisions of an open-source post-quantum HSM chip — ML-KEM-512 NTT and Keccak from Python golden model to SKY130 layout
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ISSCC27: An 8-bit SAR ADC in SkyWater sky130 — two notebooks on measuring honestly
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ISSCC27: An 8-bit SAR ADC in SkyWater sky130 — two notebooks on measuring honestly
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SubVGA: A SPICE-Validated $g_m/I_D$ Lookup-Table Flow for a Subthreshold Current-Steering VGA in SKY130
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SubVGA: A SPICE-Validated $g_m/I_D$ Lookup-Table Flow for a Subthreshold Current-Steering VGA in SKY130
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ISSCC27: Measuring the design decisions of an open-source post-quantum HSM chip — ML-KEM-512 NTT and Keccak from Python golden model to SKY130 layout
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ISSCC27: Measuring the design decisions of an open-source post-quantum HSM chip — ML-KEM-512 NTT and Keccak from Python golden model to SKY130 layout
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Zenith-Core: 8-bit RISC-V-inspired MCU (Pablo López)
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Zenith-Core: 8-bit RISC-V-inspired MCU (Pablo López)
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ISSCC27: Comparator Atlas — schematic-to-layout decision characterization
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ISSCC27: Model2GDS — auditable model-to-RTL workflow for reproducible systolic-array design
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ISSCC27: Model2GDS — auditable model-to-RTL workflow for reproducible systolic-array design
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ISSCC27: Model2GDS — auditable model-to-RTL workflow for reproducible systolic-array design
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ISSCC27 Code-a-Chip: Flipside - a radiation-hardening library and cost–reliability explorer (Mac Rogers, UQ)
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