Bump DspTap to 0eb09fa (shared Kaiser-window Bessel series); re-record icount baselines

[tap]

What this changes

Bumps submodules/dsptap from 28a34a1 to 0eb09fa, which includes tap/DspTap#38. It then re-records bench/baselines.json on all three targets, regenerates the README icount table, and adds the docs/PERFORMANCE.md ledger entry the re-record requires. Docs that priced construction at ~1.3 G instructions now say ~0.9 G.

Why

DspTap#38 computes the Kaiser window's Bessel series once, for half the taps, and mirrors it. The coefficients are bit-identical and the filter design is 32 % cheaper on M33. Every ratchet scenario constructs a converter, so every baseline dropped beyond the two-sided ±3 % gate. The ratchet flagged all 21 as "IMPROVED beyond tolerance" before the update.

Verification

• Ratchet, before the update (constant per target across the seven scenarios, the construction-only signature):

  Target	Change per scenario
  M33	−393 to −398 M (pipeline_q15 −27.8 %)
  Hexagon	−47 M
  M55	−6 M

• Ratchet, after icount.py --update: it passes against the committed file on all three targets. The builds use CI's configure line, the same QEMU plugin-header SHA, the same toolchains (arm-none-eabi-gcc 13.2.1, hexagon-clang 19.1.5) and plugin-enabled qemu-hexagon 8.2.2.

  • My local counts equalled CI's to the instruction on M55/M33 in the last compare.yml run.
  • The PR's own ratchet job is the cross-check that these baselines match CI.

• Audio path unchanged: the comparison workloads' steady state (4 s − 2 s) is identical to the instruction on all three targets, both float and Q15.

• Construction:

  Target	float	Q15	before (float / Q15)
  M33	870 M	884 M	1,268 / 1,281 M
  Hexagon	133 M	136 M	181 / 184 M
  M55	17.3 M	18.4 M	23.6 / 24.6 M

  Full stereo converter on M33: 0.91 G (was 1.31 G).

• Host: 73/73 tests pass under GCC 13 and clang 18 with SRT_WERROR=ON and the C ABI built.

• Book: it builds with mdBook v0.4.40 with 0 warnings/errors.

• Not run locally: the M33/M55/Hexagon test legs and sanitizers, left to CI.

Notes for the reviewer

• Submodule pin moved: DspTap 28a34a1 → 0eb09fa. The range also brings DspTap's FFT stages (header-only FFT, no compiled tap_dsp_fft by default) and math.h. SampleRateTap uses neither, and the build and tests are unaffected.
• Other consumers: RatioTap also pins DspTap. Its canonical tables are compile-time, so only custom-spec runtime designs would get cheaper when it bumps.

🤖 Generated with Claude Code

https://claude.ai/code/session_01G3HxzEGiZp7jStoMuYNuBK

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