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Perpetually Debugging
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Perpetually Debugging
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Achievement: YOLOAchievement: Pull Shark

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theworldofobi/README.md

Obi Obetta (Obi++)

Welcome to my GitHub!

I am a master's student in Electrical and Computer Engineering at the University of Colorado Boulder (Class of 2028), and I received my bachelor's from the University of Chicago. My main interests are in formal verification, computer architecture, digital design, and hardware correctness! Currently on the lookout for open-source projects and internships in FPGA/ASIC design verification. I also post short-form content about hardware/firmware concepts on Instagram and on Twitter/X.

Skillset

Category Skills
Programming C++20/23, C, Python, Bash, Tcl, SystemC
HDLs SystemVerilog, VHDL, Verilog, Vitis HLS (C++)
Frameworks/Tools UVM, CoCoTB, Verilator, OpenOnload
Methodologies Constrained-Random Verification (CRV), Assertion-Based Verification (ABV), Clock Domain Crossing (CDC), Static Timing Analysis (STA)
Protocols AXI4, AXI-Stream, PCIe Gen4/5 Ethernet, DDR4/5, SR-IOV
Environments AMD Vivado, Quartus Prime, Vitis, VSCode, Neovim

Open Source Contributions

  • CuPy: cupy (Python)
  • Beman Project: beman-tidy (Python, CMake, pytest) - in progress

Pinned Loading

  1. FPGA-ASIC-Resources FPGA-ASIC-Resources Public

    A list of resources for learning about FPGAs and ASICs

  2. obipluspluslinks obipluspluslinks Public

    A repository of resources from my Obi++ social media accounts

    1

  3. neuralscale-tinytapeout neuralscale-tinytapeout Public

    A custom coprocessor block optimized for streaming matrix operations using a specialized control word format modeled after the industrial NeuralScale architecture

  4. ArtyFFT ArtyFFT Public

    An FFT filter on an Arty A7-100T using HLS C++

    Tcl

  5. ArtyLabs ArtyLabs Public

    A collection of projects on my Arty A7

  6. HDLWorld HDLWorld Public

    A collection of snippets in SystemVerilog, VHDL, and Verilog for practice and study purposes (practice platform coming soon)

    TypeScript